公开(公告)号：US07385144B2

公开(公告)日：2008-06-10

申请号：US11281797

申请日：2005-11-17

Applicant: Ronald J. Hash ,  Mitchell Percival

Inventor： Ronald J. Hash ,  Mitchell Percival

IPC: H05K1/03 ,  H05K3/10

CPC classification number: H05K3/366 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/09145 ,  H05K2201/09181 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09709 ,  Y10T29/49165 ,  Y10T29/49798

Abstract: A method and apparatus is provided for forming a printed circuit board or other panel in which an array of vias are arranged in a desired connection grid within one or more layers of the board and then the board and vias are cut to form an edge of the board where a surface of the vias is exposed. The board may be orthogonally mounted on its edge to another thin circuit board or aperture sheet with the exposed surface of each via directly connected to such other board or sheet.

Abstract translation: 提供了一种用于形成印刷电路板或其他面板的方法和装置，其中通孔阵列布置在板的一层或多层内的所需连接格栅中，然后将板和通孔切割成形成 通孔的表面露出的板。 该板可以在其边缘上正交地安装到另一个薄的电路板或孔板上，每个通孔的暴露表面直接连接到这样的其它板或片。

公开(公告)号：US20080123308A1

公开(公告)日：2008-05-29

申请号：US12023616

申请日：2008-01-31

Applicant: Chang Sup Ryu ,  Myung Sam Kang

Inventor： Chang Sup Ryu ,  Myung Sam Kang

IPC: H05K7/06

CPC classification number: H05K1/185 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/49101 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Disclosed is a PCB including an embedded passive component and a method of fabricating the same. The PCB includes at least two circuit layers in which circuit patterns are formed. At least one insulating layer is interposed between the circuit layers. A pair of terminals is vertically formed through the insulating layers, plated with a first conductive material, and separated from each other by a predetermined distance. The embedded passive component is interposed between the terminals and has electrodes formed on both sides thereof. The electrodes are separated from the terminals by a predetermined distance and electrically connected to the terminals through a second conductive material.

Abstract translation: 公开了一种包括嵌入式无源元件的PCB及其制造方法。 PCB包括形成电路图案的至少两个电路层。 在电路层之间插入至少一个绝缘层。 一对端子通过绝缘层垂直地形成，电镀有第一导电材料，并且彼此分开预定距离。 嵌入式无源部件插入在端子之间，并且具有形成在其两侧的电极。 电极与端子分开预定距离，并通过第二导电材料与端子电连接。

公开(公告)号：US07371970B2

公开(公告)日：2008-05-13

申请号：US10731390

申请日：2003-12-08

Applicant: Jeffrey D. Flammer ,  Robert Forcier

Inventor： Jeffrey D. Flammer ,  Robert Forcier

IPC: H05K1/03

CPC classification number: H05K3/4691 ,  H05K1/0278 ,  H05K1/118 ,  H05K1/16 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/0061 ,  H05K3/429 ,  H05K2201/09036 ,  H05K2201/09081 ,  H05K2201/0909 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/09745 ,  H05K2203/1572 ,  H05K2203/302 ,  Y10T29/49126

Abstract: A rigid-flex circuit board system that can be manufactured using less expensive and more reliable rigid circuit board methods and equipment, and can maintain rigidity and dimensional stability until the time when it is first desired to flex.

Abstract translation: 可以使用更便宜和更可靠的刚性电路板方法和设备制造的刚性 - 柔性电路板系统，并且可以保持刚性和尺寸稳定性，直到首次需要弯曲时为止。

公开(公告)号：US07350296B2

公开(公告)日：2008-04-01

申请号：US11020466

申请日：2004-12-22

Applicant: Chang Sup Ryu ,  Myung Sam Kang

Inventor： Chang Sup Ryu ,  Myung Sam Kang

IPC: H01K3/10

CPC classification number: H05K1/185 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/49101 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Disclosed is a method of fabricating a PCB including an embedded passive component and a method of fabricating the same and a method of fabricating the same. The PCB includes at least two circuit layers in which circuit patterns are formed. At least one insulating layer is interposed between the circuit layers. A pair of terminals is vertically formed through the insulating layers, plated with a first conductive material, and separated from each other by a predetermined distance. The embedded passive component is interposed between the terminals and has electrodes formed on both sides thereof. The electrodes are separated from the terminals by a predetermined distance and electrically connected to the terminals through a second conductive material.

Abstract translation: 公开了一种制造包括嵌入式无源元件的PCB的方法及其制造方法及其制造方法。 PCB包括形成电路图案的至少两个电路层。 在电路层之间插入至少一个绝缘层。 一对端子通过绝缘层垂直地形成，电镀有第一导电材料，并且彼此分开预定距离。 嵌入式无源部件插入在端子之间，并且具有形成在其两侧的电极。 电极与端子分开预定距离，并通过第二导电材料与端子电连接。

公开(公告)号：US20080073107A1

公开(公告)日：2008-03-27

申请号：US11854012

申请日：2007-09-12

Applicant: Mitsuru HONJO

Inventor： Mitsuru HONJO

IPC: H05K1/00

CPC classification number: H05K1/024 ,  H05K1/115 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09336 ,  H05K2201/09536 ,  H05K2203/063

Abstract: A first wiring pattern and a second ground layer are formed on one surface of a base insulating layer, and a second wiring pattern and a first ground layer are formed on the other surface of the base insulating layer. A metal plating layer connecting the first and second wiring patterns to each other is formed in a through hole of the base insulating layer. A cover insulating layer is formed on the other surface of the base insulating layer so as to cover the first ground layer and the second wiring pattern and has a through hole on an area opposite to a part of the first wiring pattern. A high dielectric insulator is formed in the through hole of the cover insulating layer.

Abstract translation: 第一布线图案和第二接地层形成在基底绝缘层的一个表面上，并且第二布线图案和第一接地层形成在基底绝缘层的另一个表面上。 在基底绝缘层的通孔中形成有连接第一和第二布线图案的金属镀层。 覆盖绝缘层形成在基底绝缘层的另一个表面上，以覆盖第一接地层和第二布线图案，并且在与第一布线图案的一部分相对的区域上具有通孔。 在绝缘层的通孔中形成高介电绝缘体。

公开(公告)号：US20080022519A1

公开(公告)日：2008-01-31

申请号：US11865794

申请日：2007-10-02

Applicant: Donald Farquhar ,  James Herard ,  Michael Klodowski ,  David Questad ,  Der-jin Woan

Inventor： Donald Farquhar ,  James Herard ,  Michael Klodowski ,  David Questad ,  Der-jin Woan

IPC: H05K3/36

CPC classification number: H05K3/4641 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/068 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A laminating method. A structure that includes first and second dielectric layers respectively positioned on opposing surfaces of a thermally conductive layer is pressurized between 1000 and 3000 psi concurrent with being subjected to a thermal process, including the steps of: (a) heating the structure from ambient room temperature to a temperature between 670° F. to 695° F. in a heatup stage of duration 42 to 57 minutes; (b) after step (a), maintaining the structure at an approximately constant temperature between 670° F. and 695° F. in a dwell stage of duration 105 to 125 minutes; (c) after step (b), cooling the structure to 400° F. in a slow cool stage of duration of 120 to 150 minutes, wherein step (c) is performed after step (b); and (d) after step (3), cooling the structure to ambient room temperature in a rapid cool stage of duration less than 180 minutes.

Abstract translation: 层压方法。 包括分别位于导热层的相对表面上的第一和第二电介质层的结构在1000和3000psi之间被加压，同时进行热处理，包括以下步骤：（a）从环境室温 在持续时间为42至57分钟的加热阶段中温度在670°F至695°F之间; （b）在步骤（a）之后，在持续105至125分钟的停留阶段中，将结构保持在670°F和695°F之间的近似恒定温度; （c）在步骤（b）之后，在120至150分钟的缓慢冷却阶段中将结构冷却至400°F，其中步骤（c）在步骤（b）之后进行; 和（d）在步骤（3）之后，在持续时间小于180分钟的快速冷却阶段中将结构冷却至环境室温。

公开(公告)号：US20070278644A1

公开(公告)日：2007-12-06

申请号：US11756403

申请日：2007-05-31

Applicant: Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

Inventor： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

IPC: H01L23/02

CPC classification number: H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/19041 ,  H05K1/186 ,  H05K3/323 ,  H05K3/4602 ,  H05K3/4614 ,  H05K2201/09536 ,  H05K2203/061 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stack structure of circuit boards embedded with semiconductor components therein is proposed, which includes at least two semiconductor components embedded circuit boards, a plurality of conductive bumps, and at least one adhesive layer. The circuit boards are each formed with a circuit layer having a plurality of electrical connection pads. The conductive bumps are formed on the electrical connection pads of at least one of the circuit boards. The adhesive layer is formed between the circuit boards such that a portion of the adhesive layer between the conductive bumps and the electrical connection pads, or between the opposing conductive bumps, forms a conductive channel and thereby forms an electrical connection between the circuit boards.

Abstract translation: 提出了嵌入其中的半导体部件的电路板的堆叠结构，其包括至少两个半导体部件嵌入式电路板，多个导电凸块和至少一个粘合剂层。 电路板各自形成有具有多个电连接焊盘的电路层。 导电凸块形成在至少一个电路板的电连接焊盘上。 粘合剂层形成在电路板之间，使得导电凸块和电连接焊盘之间或相对的导电凸块之间的粘合剂层的一部分形成导电通道，从而在电路板之间形成电连接。

公开(公告)号：US20070266886A1

公开(公告)日：2007-11-22

申请号：US11736495

申请日：2007-04-17

Applicant: Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

Inventor： Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

IPC: C09D5/00

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

Abstract translation: 本发明的目的是提供一种制造多层印刷电路板的方法，其能够同时通孔填充和形成导体电路，并且可以在基板和高密度布线上构造具有良好结晶度和均匀沉积的通孔 并且可以实现高可靠性的导体连接而不退火。 本发明涉及一种多层印刷电路板的制造方法，其特征在于，在形成有导体电路的基板上设置层间树脂绝缘层，在所述层间树脂绝缘层上形成用于形成通孔的开口，形成无电镀金属 层，在其上设置抗蚀剂，进行电镀，剥离抗蚀剂并蚀刻无电镀金属层以提供导体电路和通孔，其中使用所述无电镀金属层作为阴极间歇地进行电镀 以及在所述阳极和所述阴极之间的恒定电压下的电镀金属作为阳极。

公开(公告)号：US07279412B2

公开(公告)日：2007-10-09

申请号：US10717977

申请日：2003-11-20

Applicant: Jee-Soo Mok ,  Byung-Kook Sun ,  Chang-Kyu Song ,  Geum-Hee Yun ,  Tae-Hoon Kim

Inventor： Jee-Soo Mok ,  Byung-Kook Sun ,  Chang-Kyu Song ,  Geum-Hee Yun ,  Tae-Hoon Kim

IPC: H01L21/4763 ,  H05K3/00

CPC classification number: H05K3/462 ,  H05K3/4069 ,  H05K3/4638 ,  H05K2201/09536 ,  H05K2201/10378 ,  H05K2203/0191 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed are a multi-layer printed circuit board and a method for manufacturing the multi-layer printed circuit board. Circuit layers and insulating layers are alternately stacked so that via holes of the circuit layers provided with plated inner walls without application of additional plating and conductive paste-filling steps are connected to via holes of the insulating layers filled with a conductive paste.

Abstract translation: 公开了一种多层印刷电路板和制造多层印刷电路板的方法。 交替堆叠电路层和绝缘层，使得没有施加附加电镀和导电糊料填充步骤的设置有镀覆内壁的电路层的通孔连接到填充有导电浆料的绝缘层的通孔。

公开(公告)号：US20070217168A1

公开(公告)日：2007-09-20

申请号：US11752032

申请日：2007-05-22

Applicant: Jinsaku Masuyama ,  Rajen Murugan

Inventor： Jinsaku Masuyama ,  Rajen Murugan

IPC: H05K7/06

CPC classification number: H05K1/115 ,  H05K1/0237 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09645 ,  Y10T29/49124

Abstract: A system, apparatus and method for controlled impedance at transitional via sites using barrel inductance minimization are provided. In one embodiment, one or more sidewalls of a via barrel are preferably processed such that conductive material disposed thereon is selectively removed thereby forming an inner-via trace connecting one or more conductive traces and/or pads on a first substrate layer to one or more conductive traces and/or pads on a second substrate layer. Removal of conductive material from a sidewall of the via barrel is done in a manner such that an inner-via trace traveling from a first surface to a second surface of one or more substrate layers possesses at least one electrical characteristic substantially approximating a corresponding electrical characteristic of those structures to which the inner-via trace is connected.

Abstract translation: 提供了一种使用筒电感最小化的过渡通过位置处的受控阻抗的系统，装置和方法。 在一个实施例中，通孔筒的一个或多个侧壁优选地被加工成使得选择性地去除布置在其上的导电材料，从而形成将第一衬底层上的一个或多个导电迹线和/或焊盘连接到一个或多个 导电迹线和/或第二基底层上的焊盘。 从通孔筒的侧壁去除导电材料以这样的方式进行，使得从一个或多个基底层的第一表面到第二表面行进的内部通孔迹线具有至少一个电特性，其基本上接近相应的电特性 内部通孔迹线连接到的那些结构。