公开(公告)号：US08575496B2

公开(公告)日：2013-11-05

申请号：US13269079

申请日：2011-10-07

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/16 ,  H05K1/18

CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K1/112 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/166

Abstract: A multilayer printed wiring board including a layered capacitor section provided on a first interlayer resin insulation layer and a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. A second interlayer resin insulation layer is provided on the first insulation layer and the capacitor section, and a metal thin-film layer is provided over the capacitor section and on the second insulation layer. An outermost interlayer resin insulation layer is provided on the second insulation layer and the metal thin-film layer. A mounting section is provided on the outermost insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals. Second via conductors electrically connect the second layered electrode to the second external terminals.

Abstract translation: 一种多层印刷线路板，包括设置在第一层间树脂绝缘层和高电介质层上的层状电容器部分和夹着高电介质层的第一和第二层状电极。 在第一绝缘层和电容器部分上设置第二层间树脂绝缘层，并且在电容器部分和第二绝缘层上设置金属薄膜层。 在第二绝缘层和金属薄膜层上设置最外层的层间树脂绝缘层。 安装部分设置在最外层绝缘层上，并且具有安装半导体元件的第一和第二外部端子。 多个通孔导体穿过每个绝缘层。 通孔导体包括将第一层状电极电连接到第一外部端子的第一通孔导体。 第二通孔导体将第二层状电极电连接到第二外部端子。

公开(公告)号：US20130215588A1

公开(公告)日：2013-08-22

申请号：US13756994

申请日：2013-02-01

Applicant: FUJITSU LIMITED

Inventor： Kenichi Kawai

IPC: H05K1/02

CPC classification number: H05K1/0298 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/116 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09718

Abstract: A multilayered wiring substrate that includes at least one signal layer and at least one ground layer is provided. The multilayered wiring substrate includes a first signal via that extends in a direction substantially perpendicular to the layers of the multilayered wiring substrate, is conductively connected to one of a pair of differential signaling wires provided in the signal layer, and is formed on a first grid point; and a second signal via that extends in a direction substantially perpendicular to the layers of the multilayered wiring substrate, is conductively connected to the other of the pair of differential signaling wires, and is formed on a second grid point that is positioned diagonally adjacent with respect to the first signal via.

Abstract translation: 提供了包括至少一个信号层和至少一个接地层的多层布线基板。 所述多层布线基板包括沿着与所述多层布线基板的层基本垂直的方向延伸的第一信号通路，导电地连接到设置在所述信号层中的一对差动信号线之一，并形成在第一格栅 点; 并且在与多层布线基板的层基本垂直的方向上延伸的第二信号通路导电地连接到该对差分信号线中的另一个，并且形成在相对于第二格栅点对角地相邻位置 到第一个信号通过。

公开(公告)号：US08487195B2

公开(公告)日：2013-07-16

申请号：US12717570

申请日：2010-03-04

Applicant: Shengli Lin

Inventor： Shengli Lin

IPC: H05K1/11

CPC classification number: H05K1/162 ,  H05K1/0222 ,  H05K1/0251 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09781

Abstract: A via structure is disclosed to pass electronic signals from a first conductive pathway formed on a first outermost substrate of a multi-layer PCB to a second conductive pathway formed on a second outermost substrate of the multi-layer PCB. The via structure allows the electronic signals to pass from the first outermost substrate through one or more inner substrates to the second outermost substrate. The one or more inner substrates include one or more closed geometric structures to enclose the via structure.

Abstract translation: 公开了一种通孔结构，用于将形成在多层PCB的第一最外层衬底上的第一导电通路的电子信号传递到形成在多层PCB的第二最外层衬底上的第二导电通路。 通孔结构允许电子信号从第一最外面的衬底通过一个或多个内部衬底到第二最外面的衬底。 一个或多个内部基板包括一个或多个闭合的几何结构以封闭通孔结构。

公开(公告)号：US08431834B2

公开(公告)日：2013-04-30

申请号：US12485375

申请日：2009-06-16

Applicant: Craig Twardy ,  Robert McDonald

Inventor： Craig Twardy ,  Robert McDonald

IPC: H05K1/11

CPC classification number: H05K3/0047 ,  G01R31/024 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0268 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/175 ,  Y10T29/49117

Abstract: A method is disclosed for fabricating a PCB so that is can easily be determined if a via in the PCB has not been counterbored to a desired depth. A PCB fabricated according to the method also is disclosed.

Abstract translation: 公开了一种用于制造PCB的方法，使得如果PCB中的通孔没有被吸入到期望的深度，则可以容易地确定。 公开了根据该方法制造的PCB。

公开(公告)号：US20130000956A1

公开(公告)日：2013-01-03

申请号：US13616174

申请日：2012-09-14

Applicant: Yoshiyuki ISHIDA ,  Sadao Matsushima ,  Toshihide Fukuchi

Inventor： Yoshiyuki ISHIDA ,  Sadao Matsushima ,  Toshihide Fukuchi

IPC: H05K1/02

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/642 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/0367 ,  H05K2201/093 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09854 ,  H05K2201/10098 ,  H01L2924/00

Abstract: A high-frequency circuit board capable of easily forming a bias line whose resonance frequency is sufficiently separated from operating frequency is provided. On a high-frequency circuit board 100, by electrically connecting a bias line 11 to a high-frequency circuit 10 using blind via holes 106 and 107, it is possible to limit the route that has a possibility of producing resonance only to the bias line connecting the ends 106a and 107a of the blind via holes 106 and 107 to the bias line 11. By adjusting the route length from the end 106a to the end 107a, it is possible to prevent production of resonance in the vicinity of the operating frequency.

Abstract translation: 提供了能够容易地形成谐振频率与工作频率充分分离的偏置线的高频电路基板。 在高频电路板100上，通过使用盲通孔106和107将偏置线11与高频电路10进行电连接，可以限制仅具有产生谐振的可能性的路径到偏置线 将盲孔106和107的端部106a和107a连接到偏置线11.通过调整从端部106a到端部107a的路线长度，可以防止在工作频率附近产生谐振。

公开(公告)号：US08325490B2

公开(公告)日：2012-12-04

申请号：US12823316

申请日：2010-06-25

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H05K1/11

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

公开(公告)号：US20120233857A1

公开(公告)日：2012-09-20

申请号：US13442423

申请日：2012-04-09

Applicant: KAZUHIRO KASHIWAKURA

Inventor： KAZUHIRO KASHIWAKURA

IPC: H05K3/00

CPC classification number: H05K1/116 ,  H05K1/0222 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09618 ,  H05K2201/09718 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: A printed wiring board comprises ground layers stacked via insulator(s); a first through hole; second through holes; and signal wirings each extending from the first through hole through the clearance between predetermined ones of the ground layers, disposed between predetermined second through holes of the second through holes. Each of first clearances in the ground layers neighboring layer in which the signal wiring is disposed has an outline that a distance between the first through hole and outline of the first clearance is minimum of the signal wiring. Each of second clearances in the ground layers not adjacent to the signal wiring has an outline formed outside a circle connecting each center of second through holes centering the first signal through hole, such that outline of second clearance does not contact with the second through holes.

Abstract translation: 印刷电路板包括通过绝缘体堆叠的接地层; 第一个通孔; 第二通孔; 以及信号布线，其各自从第一通孔延伸穿过位于第二通孔的预定第二通孔之间的预定接地层之间的间隙。 其中布置信号布线的地层相邻层中的每个第一间隙具有第一通孔之间的距离和第一间隙的轮廓线是信号布线最小的轮廓。 与信号线不相邻的接地层中的每个第二间隙具有形成在连接第一通孔的中心的第二通孔的圆周外的轮廓，使得第二间隙的轮廓不与第二通孔接触。

公开(公告)号：US20120228015A1

公开(公告)日：2012-09-13

申请号：US13346738

申请日：2012-01-10

Applicant: Chung W. Ho

Inventor： Chung W. Ho

IPC: H05K1/16 ,  H05K3/10 ,  H05K3/46 ,  H05K3/30 ,  H05K3/06 ,  H05K3/36 ,  H05K1/00 ,  H05K3/42

CPC classification number: H05K1/185 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/25 ,  H01L24/82 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/2518 ,  H01L2224/82005 ,  H01L2924/12042 ,  H05K1/116 ,  H05K3/0097 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09718 ,  H05K2203/1469 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A process of electronic structure is provided. First, a carrier board is provided, in which the carrier board has a first surface. Next, a first release layer is formed on the first surface of the carrier board. The first release layer has property of withstanding high-temperature and temporary adhesion capability and the first release layer entirely or mostly overlays the first surface. Then, a built-up structure is formed on the first release layer. Finally, a separating process is performed so that the built-up structure is separated from the carrier board to form an electronic structure.

Abstract translation: 提供电子结构的过程。 首先，提供载体板，其中承载板具有第一表面。 接下来，在载板的第一表面上形成第一释放层。 第一释放层具有耐高温和临时粘合能力的特性，并且第一释放层完全或大体上覆盖在第一表面上。 然后，在第一剥离层上形成积层结构。 最后，进行分离处理，使得积层结构与载体板分离以形成电子结构。

公开(公告)号：US08183468B2

公开(公告)日：2012-05-22

申请号：US12216629

申请日：2008-07-08

Applicant: Han Kim ,  Dae-Hyun Park

Inventor： Han Kim ,  Dae-Hyun Park

IPC: H05K1/11

CPC classification number: H01Q15/008 ,  H01P1/2005 ,  H01Q15/006 ,  H05K1/0236 ,  H05K1/0237 ,  H05K1/116 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4652 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09663 ,  H05K2201/09718 ,  Y10T29/49165

Abstract: An electromagnetic bandgap structure and a printed circuit board including it as well as a method of manufacturing thereof that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. The electromagnetic bandgap structure in accordance with an embodiment of the present invention can include: a first metal layer; a first dielectric layer, stacked on the first metal layer; a metal plate, stacked on the first dielectric layer; a second dielectric layer, stacked on the metal plate and the first dielectric layer; a second metal layer, stacked on the second dielectric layer; and a via, directed from the metal plate to the first metal layer and the second metal layer. The via can be connected to the first metal layer and is not connected the second metal layer.

Abstract translation: 公开了电磁带隙结构和包括它的印刷电路板及其制造方法，其可以解决模拟电路和数字电路之间的混合信号问题。 根据本发明的实施例的电磁带隙结构可以包括：第一金属层; 第一介电层，堆叠在第一金属层上; 金属板，堆叠在第一介电层上; 第二电介质层，堆叠在所述金属板和所述第一介电层上; 第二金属层，堆叠在第二介电层上; 以及从金属板引导到第一金属层和第二金属层的通孔。 通孔可以连接到第一金属层，并且不连接到第二金属层。

公开(公告)号：US08164005B2

公开(公告)日：2012-04-24

申请号：US12099875

申请日：2008-04-09

Applicant: Yuusuke Yamashita ,  Ryota Suzuki ,  Masahiro Tanabe ,  Taihei Nakada ,  Tsuyoshi Kumamoto

Inventor： Yuusuke Yamashita ,  Ryota Suzuki ,  Masahiro Tanabe ,  Taihei Nakada ,  Tsuyoshi Kumamoto

IPC: H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0222 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

Abstract: A multilayer high-frequency circuit board includes a signal line, ground layers, and an interlayer circuit. A signal line where a high-frequency signal flows is formed in the signal line layer. The ground layers are laminated on both sides of the signal line layer, each of which is grounded. The interlayer circuit is provided in the signal line layer and includes a ground connecting portion connected to the ground layers and a signal line connecting portion connected to the signal line. One of the signal line connecting portion and the ground connecting portion surrounds an outer periphery of the other of the signal line connecting portion and the ground connecting portion concentrically with the one being separated from the outer periphery of the other along the signal line layer. An inner periphery of the one and the outer periphery of the other have a similar shape excluding a complete circle.

Abstract translation: 多层高频电路板包括信号线，接地层和层间电路。 在信号线层中形成高频信号流动的信号线。 接地层层叠在信号线层的两侧，每一个都接地。 层间电路设置在信号线层中，并且包括连接到接地层的接地连接部分和连接到信号线的信号线连接部分。 信号线连接部分和接地连接部分之一围绕信号线连接部分和接地连接部分的另一个的外周围同步地沿着信号线层与另一个的外周分离。 另一个的一个和外周的内周具有除完整圆之外的类似形状。