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公开(公告)号：US20050207113A1
公开(公告)日：2005-09-22
申请号：US11120979
申请日：2005-05-04
Applicant: Atsuko Tanaka , Masuo Ohnishi
Inventor： Atsuko Tanaka , Masuo Ohnishi
IPC: G06F1/20 , H01L23/467 , H01R4/48 , H05K1/02 , H05K7/20
CPC classification number: H05K1/0272 , G06F1/203 , H01L2924/0002 , H05K1/0209 , H05K2201/064 , H05K2201/09072 , H05K2201/09772 , H05K2201/09781 , H01L2924/00
Abstract: A fan housing of a fan unit includes a housing wall standing from the surface of a printed circuit board. The printed circuit board serves to establish the fan housing in cooperation with the housing wall. The fan housing further includes a ceiling wall connected to the housing wall. The ceiling wall extends along a datum plane parallel to the surface of the printed circuit board. A high speed airflow can be generated within the fan housing. The airflow promotes the heat radiation from the printed circuit board. An electrically conductive wiring pattern extending over the surface of the printed circuit board may further promote the heat radiation from the printed circuit board.
Abstract translation: 风扇单元的风扇壳体包括从印刷电路板的表面竖立的壳体壁。 印刷电路板用于与壳体壁一起建立风扇壳体。 风扇壳体还包括连接到壳体壁的顶壁。 顶壁沿平行于印刷电路板表面的基准平面延伸。 风扇外壳内可能产生高速气流。 气流促进印刷电路板的热辐射。 在印刷电路板的表面上延伸的导电布线图形可以进一步促进来自印刷电路板的热辐射。
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公开(公告)号：US20050189645A1
公开(公告)日：2005-09-01
申请号：US11058810
申请日：2005-02-15
Applicant: Akira Nakano , Yoshiomi Tsuji , Yoshinari Higa
Inventor： Akira Nakano , Yoshiomi Tsuji , Yoshinari Higa
CPC classification number: H05K1/162 , G11B5/40 , G11B5/486 , H01L2224/16 , H05K1/113 , H05K1/189 , H05K3/28 , H05K2201/0317 , H05K2201/09763 , H05K2201/09772 , H05K2201/10674
Abstract: A flexible printed circuit board includes a substrate layer composed of insulating material, a protection circuit of a thin-film capacitor element, the protection circuit including a first wiring layer on the substrate layer, a dielectric layer, and a counter electrode layer. At least a portion of each of the first wiring layer and the counter electrode layer serves as a terminal. The front surface of each of the first wiring layer and the counter electrode layer, except the terminal portion, is covered with an insulating coating.
Abstract translation: 柔性印刷电路板包括由绝缘材料构成的衬底层，薄膜电容器元件的保护电路，保护电路包括在衬底层上的第一布线层，电介质层和对电极层。 第一布线层和对电极层的至少一部分用作端子。 除了端子部分之外，第一布线层和对电极层中的每一个的前表面被绝缘涂层覆盖。
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公开(公告)号：US06909604B2
公开(公告)日：2005-06-21
申请号：US10664933
申请日：2003-09-22
Applicant: Atsuko Tanaka , Masuo Ohnishi
Inventor： Atsuko Tanaka , Masuo Ohnishi
IPC: G06F1/20 , H01L23/467 , H01R4/48 , H05K1/02 , H05K7/20
CPC classification number: H05K1/0272 , G06F1/203 , H01L2924/0002 , H05K1/0209 , H05K2201/064 , H05K2201/09072 , H05K2201/09772 , H05K2201/09781 , H01L2924/00
Abstract: A fan housing of a fan unit includes a housing wall standing from the surface of a printed circuit board. The printed circuit board serves to establish the fan housing in cooperation with the housing wall. The fan housing further includes a ceiling wall connected to the housing wall. The ceiling wall extends along a datum plane parallel to the surface of the printed circuit board. A high speed airflow can be generated within the fan housing. The airflow promotes the heat radiation from the printed circuit board. An electrically conductive wiring pattern extending over the surface of the printed circuit board may further promote the heat radiation from the printed circuit board.
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114.发明授权公开(公告)号：US06901343B2
公开(公告)日：2005-05-31
申请号：US10029571
申请日：2001-12-20
Applicant: Eiji Takahashi , Yukihiro Fukumoto , Yoshiyuki Saito , Osamu Shibata , Shinichi Tanimoto , Takeshi Nakayama
Inventor： Eiji Takahashi , Yukihiro Fukumoto , Yoshiyuki Saito , Osamu Shibata , Shinichi Tanimoto , Takeshi Nakayama
CPC classification number: G06F17/5068 , H05K1/0275 , H05K1/0298 , H05K1/114 , H05K2201/09627 , H05K2201/09772 , H05K2201/10151
Abstract: A signal line, being in a six-layer board and connecting terminal 102 of component 101 with terminal 115 of component 114, requires tamper-resistance. The signal line is composed of foil 103 on an outside layer, a via 104, foil 111 on the third layer, via 105, foil 112 on the fourth layer, via 106, and foil 113 on the sixth layer. Portions of the signal line that exist on outside layers are all hidden under circuit components. Foil 103 and an end of via 104 are placed under component 101 on first layer 116, an end of via 105 is placed under component 107 on layer 116, an end of via 106 is placed under component 108 on layer 116, the other end of via 104 is placed under component 109 on sixth layer 121, the other end of via 105 is placed under component 110 on layer 121, and foil 113 and the other end of via 106 are placed under component 114 on layer 121.
Abstract translation: 在组件101的六层板和连接端子102与元件114的端子115之间的信号线需要防篡改。 信号线由外层的箔103，通孔104，第三层上的箔111，通孔105，第四层上的箔112，第106层和第六层上的箔113组成。 存在于外层的信号线部分都隐藏在电路元件下面。 箔103和通孔104的末端放置在第一层116上的部件101下方，通孔105的端部放置在层116上的部件107的下方，通孔106的端部放置在层116上的部件108的下方，另一端 通孔104被放置在第六层121上的部件109的下方，通孔105的另一端被放置在层121上的部件110下方，并且箔113和通孔106的另一端放置在层121上的部件114下方。
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115.发明申请公开(公告)号：US20050093114A1
公开(公告)日：2005-05-05
申请号：US10900211
申请日：2004-07-28
Applicant: Dae-Woo Son , Sa-Yoon Kang , Kwan-Jai Lee
Inventor： Dae-Woo Son , Sa-Yoon Kang , Kwan-Jai Lee
IPC: H01L21/60 , H01L23/02 , H01L23/498 , H01L23/50 , H01L23/552 , H05K1/00 , H05K1/02
CPC classification number: H01L23/552 , H01L23/4985 , H01L23/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/3011 , H01L2924/3025 , H05K1/0218 , H05K1/0393 , H05K2201/09772 , H05K2201/10681 , Y10T29/49121 , H01L2224/05599
Abstract: A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.
Abstract translation: 带状电路基板和使用该电路基板的半导体装置以及形成带状电路基板的方法可以减少或消除电磁干扰（EMI），并提供能够提供更稳定的电源电压的基板或装置。 带状电路基板可以包括形成在绝缘膜上的绝缘膜和布线图案，以限定电子器件安装区域并且包括接地电极。 磁带电路基板可以包括形成在电子器件安装区域处的接地电极图案，以便除了接地电极图案连接到接地电极之外与布线图案绝缘。
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Patent Agency Ranking
公开(公告)号：US20050033865A1
公开(公告)日：2005-02-10
申请号：US10496920
申请日：2002-11-21
CPC classification number: H05K1/181 , H05K2201/09236 , H05K2201/09772 , H05K2201/10689 , Y02P70/611
Abstract: A data bus of a DVD+RW recorder between a DSP and a SDRAM usually needs a multilayer wiring board. In order to simplify the layout of the wiring board of the data bus there is provided a method for connecting at least a first and a second integrated circuit by providing the first integrated circuit having a plurality of first logical I/O ports physically arranged in a first order at the periphery, and providing the second integrated circuit having a plurality of second logical I/O ports physically arranged in a second order at the periphery, wherein each first I/O port is to be connected to one of said second I/O ports. The first and second I/O logical ports are connected independently from the first and/or second physical order, so that connection lines do not cross each other.
Abstract translation: DSP与SDRAM之间的DVD + RW刻录机的数据总线通常需要多层布线板。 为了简化数据总线的布线板的布局，提供了一种通过提供第一集成电路来连接至少第一和第二集成电路的方法，该第一集成电路具有物理地布置在第一和第二集成电路中的多个第一逻辑I / O端口 并且提供第二集成电路，该第二集成电路具有多个第二逻辑I / O端口，该第二逻辑I / O端口在外围以二级物理地布置，其中每个第一I / O端口将被连接到所述第二I / O端口 第一和第二I / O逻辑端口独立于第一和/或第二物理顺序连接，使得连接线不互相交叉。
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公开(公告)号：US20040071035A1
公开(公告)日：2004-04-15
申请号：US10682649
申请日：2003-10-09
Inventor： Peter Poechmueller
IPC: G11C007/00
CPC classification number: G11C5/005 , G11C5/143 , G11C7/04 , H01L2924/0002 , H05K1/0206 , H05K1/0209 , H05K3/28 , H05K2201/09263 , H05K2201/09772 , H05K2201/09781 , H05K2201/0989 , H05K2201/10159 , H05K2201/2018 , H01L2924/00
Abstract: A memory module includes a board, a memory device attached to the board, and a heat dissipation means arranged between the memory device and the board.
Abstract translation: 存储器模块包括板，连接到板的存储器件，以及布置在存储器件和板之间的散热器件。
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公开(公告)号：US20040004293A1
公开(公告)日：2004-01-08
申请号：US10603812
申请日：2003-06-26
Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD
Inventor： Kei Murayama
IPC: H01L023/48 , H01L023/52 , H01L029/40
CPC classification number: H05K1/111 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L2224/16225 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , H05K3/3436 , H05K3/4602 , H05K2201/09663 , H05K2201/09772 , H05K2201/10318 , Y02P70/611 , H01L2224/0401
Abstract: A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.
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公开(公告)号：US06617676B1
公开(公告)日：2003-09-09
申请号：US09868570
申请日：2001-08-08
Applicant: Laurent Oddou , Stéphane Ayala , Michael Zafrany
Inventor： Laurent Oddou , Stéphane Ayala , Michael Zafrany
IPC: H01L2980
CPC classification number: G06K19/0775 , G06K19/07749 , H01L24/24 , H01L2224/83192 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01058 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/14 , H01L2924/181 , H05K3/28 , H05K3/284 , H05K3/305 , H05K2201/09772 , H05K2201/10727 , Y02P70/613 , Y10S257/922 , H01L2924/00
Abstract: A method for making a contactless chip card of the type having an electronic module, and an antenna connected to the module, includes the following steps: producing, on a first support sheet, the antenna with connection terminals provided at its ends; producing an insulating bridge partly covering the antenna coils except for the connection terminals; depositing a drop of filling material on the insulating bridge; transferring the electronic module, with its connection pads being oriented towards the insulating bridge; and providing an electric connection between the module contact pads and the antenna connection terminals.
Abstract translation: 一种用于制造具有电子模块的类型的非接触式芯片卡的方法和连接到模块的天线，包括以下步骤：在第一支撑片上制造具有设置在其端部的连接端子的天线; 制造除了连接端子以外部分地覆盖天线线圈的绝缘桥; 在绝缘桥上沉积一滴填充材料; 传送电子模块，其连接垫朝向绝缘桥; 并在模块接触垫和天线连接端子之间提供电连接。
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公开(公告)号：US06582238B2
公开(公告)日：2003-06-24
申请号：US09911428
申请日：2001-07-25
Applicant: Takanori Unou , Hiroyuki Kawata , Kimio Kobayashi
Inventor： Takanori Unou , Hiroyuki Kawata , Kimio Kobayashi
IPC: H01R1200
CPC classification number: H05K1/0231 , H01L2924/0002 , H05K1/111 , H05K2201/094 , H05K2201/09772 , H05K2201/09781 , H05K2201/10522 , H05K2201/10636 , H05K2201/10689 , Y02P70/611 , H01L2924/00
Abstract: Plural pins are arranged on a printed circuit board to form a generally square shape and are electrically connected to terminals of a QFP-IC. In the pins, a pin disposed at a corner portion of the generally square shape is used as a GND terminal, and a pin adjoining the GND terminal is used as a source terminal. A conductive region is provided to extend radially from the corner portion, and is electrically connected to the ground terminal. Further, another conductive region is provided in the generally square shape and is electrically connected to the radial conductive region.
Abstract translation: 多个引脚布置在印刷电路板上以形成大致正方形形状并且电连接到QFP-IC的端子。 在引脚中，将设置在大致正方形的角部的引脚用作GND端子，并且使用与GND端子相邻的引脚作为源极端子。 导电区域被设置为从角部径向延伸，并且电连接到接地端子。 此外，另一个导电区域设置成大致正方形形状并且电连接到径向导电区域。
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