公开(公告)号：US06693359B1

公开(公告)日：2004-02-17

申请号：US10351328

申请日：2003-01-27

Applicant: Yi-Ching Lin

Inventor： Yi-Ching Lin

IPC: H01L2348

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/111 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/09436 ,  H05K2201/098 ,  Y02P70/611 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: A semiconductor package, which is to attach an electric device, such as a die, thereon and electrically connect therewith, has a substrate with a conductor pattern thereon. The conductor pattern consists of a plurality of traces in a specific layout. The conductor pattern has conducting portions on which is provided with a conductor member respectively. The conductor members locate at positions above the conducting portion of the conductor pattern with a bottom surface thereof electrically connecting a top surface of the conducting portion. A solder mask is provided on the substrate sheltering the conductor pattern but exposing at least a top surface of the conductor member. Whereby, the conductor can electrically connect the electric device via the conductor members.

Abstract translation: 在其上附着诸如模具的电气装置并与其电连接的半导体封装件具有其上具有导体图案的基板。 导体图案由特定布局中的多个迹线组成。 导体图案具有分别设有导体部件的导电部分。 导体构件位于导体图案的导电部分上方的位置处，其底表面电连接导电部分的顶表面。 在衬底上设置阻焊导体图形，但暴露于导体构件的至少顶表面的焊接掩模。 由此，导体可以经由导体构件电连接电子装置。

公开(公告)号：US06686030B2

公开(公告)日：2004-02-03

申请号：US10254724

申请日：2002-09-25

Applicant: Nobuyoshi Tsukaguchi ,  Masami Kimura

Inventor： Nobuyoshi Tsukaguchi ,  Masami Kimura

IPC: H05K102

CPC classification number: H05K3/38 ,  C04B37/021 ,  C04B37/026 ,  C04B2237/121 ,  C04B2237/125 ,  C04B2237/127 ,  C04B2237/128 ,  C04B2237/366 ,  C04B2237/402 ,  C04B2237/407 ,  C04B2237/706 ,  H01L23/3735 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/067 ,  H05K3/244 ,  H05K2201/0355 ,  H05K2201/098 ,  Y10T428/12535 ,  Y10T428/12576 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

Abstract: There is provided a metal/ceramic circuit board capable of eliminating discrepancy during mounting of parts to improve the reliability of mounting of the parts. The metal/ceramic circuit board has a ceramic substrate 10, and a metal circuit plate (a copper plate 14) bonded to the ceramic substrate 10, the metal circuit plate having a thickness of 0.1 mm to 0.5 mm, and the metal circuit plate having a skirt spreading length (a dimensional difference between the bottom and top portion of the peripheral edge portion of the metal circuit plate) of less than 50 &mgr;m.

Abstract translation: 提供了一种金属/陶瓷电路板，其能够在安装零件期间消除差异，以提高部件安装的可靠性。 金属/陶瓷电路板具有陶瓷基板10和接合到陶瓷基板10的金属电路板（铜板14），金属电路板的厚度为0.1mm〜0.5mm，金属电路板具有 裙部扩展长度（金属电路板的周边部分的底部和顶部之间的尺寸差）小于50um。

公开(公告)号：US06671949B2

公开(公告)日：2004-01-06

申请号：US09808086

申请日：2001-03-13

Applicant: Hirokazu Yoshioka ,  Norio Yoshida ,  Kenichiro Tanaka

Inventor： Hirokazu Yoshioka ,  Norio Yoshida ,  Kenichiro Tanaka

IPC: H01K310

CPC classification number: H05K3/4652 ,  H05K1/116 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/0055 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/098 ,  H05K2201/09863 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1383 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 &mgr;m in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.

Abstract translation: 多层印刷电路板形成有多个导体层，绝缘层整体层叠在一起，绝缘层中设置的非穿透通孔由导体层露出的底部，设置在通孔内部的镀层， 所述导体层之间的电连接，所述通孔形成为在通孔的内周到底面的连续区域的半径在20至100μm的范围内的轴向剖视图中的凹曲面的通孔，由此 在电镀镀层时发生的等电势面沿着连续区域弯曲，以统一电流密度，以使电镀层在厚​​度上均匀，而不会在连续区域变薄。

公开(公告)号：US06586783B2

公开(公告)日：2003-07-01

申请号：US10059359

申请日：2002-01-31

Applicant: Benoît Boursat ,  Emmanuel Dutarde ,  Nathalie Martin ,  Pierre Solomalala ,  José Saiz

Inventor： Benoît Boursat ,  Emmanuel Dutarde ,  Nathalie Martin ,  Pierre Solomalala ,  José Saiz

IPC: H01L2710

CPC classification number: H05K1/0265 ,  H01L23/3735 ,  H01L23/473 ,  H01L23/538 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/181 ,  H05K3/244 ,  H05K2201/064 ,  H05K2201/098 ,  H01L2924/00

Abstract: An electronic power circuit substrate including a wafer of electrically insulating material, wherein said wafer presents a face supporting one or more conductive tracks directly connected to one or more electronic power components, said conductive tracks being obtained by fine metallization of said face to a thickness that is less than 150 &mgr;m.

Abstract translation: 一种包括电绝缘材料晶片的电子电路电路基板，其中所述晶片呈现一个支撑直接连接到一个或多个电子元件的一个或多个导电轨道的表面，所述导电轨迹是通过所述面的精细金属化得到的， 小于150妈妈。

公开(公告)号：US20030070292A1

公开(公告)日：2003-04-17

申请号：US10186712

申请日：2002-07-02

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Nobuyoshi Tatoh ,  Jun Yorita

IPC: H05K003/02 ,  H05K003/10

CPC classification number: H01L23/498 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/30107 ,  H01S5/02 ,  H05K1/0306 ,  H05K1/167 ,  H05K3/062 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/0125 ,  H05K2201/098 ,  H05K2203/0597 ,  H05K2203/1105 ,  H05K2203/1184 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2924/01033 ,  H01L2224/45099

Abstract: A circuit board comprising a patterned first metal layer 14 formed on a ceramic substrate 11, a patterned second metal layer 16 formed on the first metal layer, and a third metal layer 17 formed covering the entire upper surface and side surfaces of the second metal layer and a part of the upper surface of the first metal layer, wherein portions of the first metal layer not covered by the third metal layer are reduced in width by etching. The circuit board has thick-film fine wiring patterns with high bonding strength between the wiring patterns and the substrate and high reliability and enables realization of high-output modules which are small in size and high in performance, by mounting at least one high-output semiconductor element thereon.

Abstract translation: 一种电路板，包括形成在陶瓷基板11上的图案化第一金属层14，形成在第一金属层上的图案化第二金属层16，以及覆盖第二金属层的整个上表面和第二金属层的整个表面的第三金属层17 以及第一金属层的上表面的一部分，其中未被第三金属层覆盖的第一金属层的部分通过蚀刻而减小宽度。 电路板具有在布线图案和基板之间具有高结合强度的厚膜精细布线图案，并且具有高可靠性，并且能够实现尺寸小且性能高的高输出模块，通过安装至少一个高输出 半导体元件。

公开(公告)号：US20030068537A1

公开(公告)日：2003-04-10

申请号：US10254724

申请日：2002-09-25

Inventor： Nobuyoshi Tsukaguchi ,  Masami Kimura

IPC: B32B003/00

CPC classification number: H05K3/38 ,  C04B37/021 ,  C04B37/026 ,  C04B2237/121 ,  C04B2237/125 ,  C04B2237/127 ,  C04B2237/128 ,  C04B2237/366 ,  C04B2237/402 ,  C04B2237/407 ,  C04B2237/706 ,  H01L23/3735 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/067 ,  H05K3/244 ,  H05K2201/0355 ,  H05K2201/098 ,  Y10T428/12535 ,  Y10T428/12576 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

Abstract: There is provided a metal/ceramic circuit board capable of eliminating discrepancy during mounting of parts to improve the reliability of mounting of the parts. The metal/ceramic circuit board has a ceramic substrate 10, and a metal circuit plate (a copper plate 14) bonded to the ceramic substrate 10, the metal circuit plate having a thickness of 0.1 mm to 0.5 mm, and the metal circuit plate having a skirt spreading length (a dimensional difference between the bottom and top portion of the peripheral edge portion of the metal circuit plate) of less than 50 nullm.

Abstract translation: 提供了一种金属/陶瓷电路板，其能够在安装零件期间消除差异，以提高部件安装的可靠性。 金属/陶瓷电路板具有陶瓷基板10和接合到陶瓷基板10的金属电路板（铜板14），金属电路板的厚度为0.1mm〜0.5mm，金属电路板具有 裙部扩展长度（金属电路板的周边部分的底部和顶部之间的尺寸差）小于50um。

公开(公告)号：US20030005582A1

公开(公告)日：2003-01-09

申请号：US10187379

申请日：2002-07-02

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Nobuyoshi Tatoh ,  Jun Yorita

IPC: H05K001/03 ,  H05K003/30 ,  H05K003/02

CPC classification number: H05K3/108 ,  H01L21/4846 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49866 ,  H01L2224/11831 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/1305 ,  H01L2924/13055 ,  H05K1/0306 ,  H05K1/167 ,  H05K3/062 ,  H05K3/388 ,  H05K2201/098 ,  H05K2203/0597 ,  H05K2203/1184 ,  Y10T29/4913 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2924/01033 ,  H01L2224/45099

Abstract: A circuit board comprising a first metal layer formed in patterns on a ceramic substrate, a second metal layer formed in patterns on the first metal layer, and a third metal layer formed covering the top surface of the second metal layer and the majority of the side surface, wherein the first and partial second metal layers not covered by the third metal layer are reduced in width by etching. The circuit board has a fine and high-resolution wiring pattern and makes it possible to realize a miniature high-performance high-output module by mounting at least one high-output semiconductor element thereon.

Abstract translation: 一种电路板，包括在陶瓷基板上以图案形成的第一金属层，在第一金属层上以图案形成的第二金属层，以及形成为覆盖第二金属层的顶表面的第三金属层， 表面，其中未被第三金属层覆盖的第一和第二金属层的宽度通过蚀刻而减小。 电路板具有精细且高分辨率的布线图案，并且可以通过在其上安装至少一个高输出半导体元件来实现微型高性能高输出模块。

公开(公告)号：US06457632B1

公开(公告)日：2002-10-01

申请号：US09619445

申请日：2000-07-19

Applicant: Kouichi Teshima ,  Emiko Higashinakagawa ,  Shinji Arai

Inventor： Kouichi Teshima ,  Emiko Higashinakagawa ,  Shinji Arai

IPC: B23K3514

CPC classification number: H05K3/3463 ,  B23K35/262 ,  H01L23/488 ,  H01L2224/16225 ,  H01L2924/12044 ,  H05K1/111 ,  H05K3/3421 ,  H05K2201/098 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T428/1266 ,  Y10T428/12708 ,  Y10T428/12715 ,  Y10T428/12792 ,  H01L2924/00

Abstract: Disclosed is a solder alloy in use for bonding electric or electronic parts, containing: 3 to 12% by weight of a zin component; and a tin component. The oxygen content of the solder alloy is reduced to 100 ppm or less. Using the solder alloy, a bonding portion is formed on the substrate and the electronic part is mounted thereon to obtain a substrate for mounting the electronic part and a substrate on which the electronic part is mounted. The bonding portion made of the above solder alloy can prevent migration.

Abstract translation: 公开了用于粘接电子或电子部件的焊料合金，其包含：3至12重量％的锌组分; 和锡组分。 焊料合金的氧含量降低到100ppm以下。 使用焊料合金，在基板上形成接合部，并且将电子部件安装在其上，以获得用于安装电子部件的基板和安装有电子部件的基板。 由上述焊料合金制成的接合部可以防止迁移。

公开(公告)号：US20020135444A1

公开(公告)日：2002-09-26

申请号：US10059623

申请日：2002-01-29

Inventor： Yutaka Ida ,  Yoshikazu Yagi ,  Tsutomu Ieki ,  Hiroaki Tanaka ,  Osamu Chikagawa

IPC: H01P003/08 ,  H01P001/203 ,  H01P007/08

CPC classification number: H01P3/081 ,  H01P1/20363 ,  H01P1/20381 ,  H01P3/088 ,  H01P7/082 ,  H01P11/003 ,  H05K1/0237 ,  H05K1/0242 ,  H05K1/162 ,  H05K3/107 ,  H05K3/4092 ,  H05K2201/037 ,  H05K2201/09036 ,  H05K2201/098 ,  H05K2201/09981

Abstract: A microstrip line includes a strip conductor, a line electrode, and edge electrodes provided at the edges on both sides of the line electrode. The construction of the microstrip line greatly reduces the edge effect of the line electrode and decreases the conductor loss of the line electrode.

Abstract translation: 微带线包括带状导体，线电极和设置在线电极两侧边缘的边缘电极。 微带线的结构大大降低了线电极的边缘效应，并降低了线电极的导体损耗。

公开(公告)号：US20020053720A1

公开(公告)日：2002-05-09

申请号：US09951391

申请日：2001-09-14

Applicant: ALSTOM

Inventor： Benoit Boursat ,  Emmanuel Dutarde ,  Luc Meysenc ,  Jose Saiz ,  Pierre Solomalala

IPC: H01L029/82

CPC classification number: H01L23/3735 ,  H01L23/147 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/13055 ,  H05K1/0306 ,  H05K3/181 ,  H05K3/244 ,  H05K2201/064 ,  H05K2201/098 ,  H01L2924/00

Abstract: A substrate for an electronic circuit, the substrate comprising a wafer of silicon Si having a top face covered in an electrically insulating layer of silicon nitride SiN, said electrically insulating layer of silicon nitride supporting one or more conductive tracks obtained by metallizing the top face of said electrically insulating layer for the purpose of enabling one or more electronic components to be connected.

Abstract translation: 一种用于电子电路的衬底，所述衬底包括具有覆盖在氮化硅SiN的电绝缘层中的顶面的硅硅晶片，所述氮化硅的电绝缘层支撑一个或多个通过金属化 所述电绝缘层用于使一个或多个电子部件能够连接。