公开(公告)号：US20090197364A1

公开(公告)日：2009-08-06

申请号：US12422428

申请日：2009-04-13

Applicant: Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

Inventor： Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

IPC: H01L21/02 ,  H01L21/78

CPC classification number: H01L23/142 ,  H01L21/6835 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/202 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.

Abstract translation: 制造衬底的方法包括以下步骤。 首先，提供具有第一表面和第二表面的金属板。 执行第一半蚀刻工艺以将金属板的第一表面蚀刻到第一深度，使得在第一表面上形成第一图案化金属层。 接下来，将第一绝缘材料沉积在第一图案化金属层中的间隙中以形成第一绝缘体。 此后，执行第二半蚀刻工艺以将金属板的第二表面蚀刻到第二深度，并且暴露第一绝缘体的至少一部分，使得在第二表面上形成第二图案化金属层。 第一深度和第二深度一起等于金属面板的厚度。

公开(公告)号：US20090179335A1

公开(公告)日：2009-07-16

申请号：US12263614

申请日：2008-11-03

Applicant: Yun-Jin OH ,  Chang-Hoon HAN ,  Kwang-Ryul LEE ,  Hyoung-Suk KIM

Inventor： Yun-Jin OH ,  Chang-Hoon HAN ,  Kwang-Ryul LEE ,  Hyoung-Suk KIM

IPC: H01L23/485 ,  H05K1/18

CPC classification number: H05K3/3452 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/15311 ,  H05K2201/09772 ,  H05K2201/09881 ,  H05K2203/0191 ,  H05K2203/049 ,  H05K2203/0577 ,  H05K2203/058 ,  H05K2203/0582 ,  H05K2203/0585 ,  H05K2203/1476 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A printed circuit board (PCB) and a semiconductor package that are configured to prevent delamination and voids. In one example embodiment, the semiconductor package includes a PCB having a base substrate on which conductive patterns are formed and which includes an interior region having a die paddle for receiving a semiconductor chip and an exterior region disposed outside the interior region. The PCB also includes a first solder resist formed on a portion of the base substrate corresponding to the interior region and a second solder resist formed on a portion of the base substrate corresponding to the exterior region. The second solder resist may also have a greater surface roughness than the surface roughness of the first solder resist.

Abstract translation: 配置为防止分层和空隙的印刷电路板（PCB）和半导体封装。 在一个示例性实施例中，半导体封装包括具有其上形成有导电图案的基底基板的PCB，其包括具有用于接收半导体芯片的管芯焊盘和设置在内部区域外部的外部区域的内部区域。 PCB还包括形成在对应于内部区域的基底基板的一部分上的第一阻焊剂和形成在对应于外部区域的基底基板的一部分上的第二阻焊剂。 第二阻焊剂也可以具有比第一阻焊剂的表面粗糙度更大的表面粗糙度。

公开(公告)号：US07421777B2

公开(公告)日：2008-09-09

申请号：US11063131

申请日：2005-02-22

Applicant: Hiroshi Asami ,  Hidetoshi Kusano ,  Yuki Nishitani ,  Ken Orui

Inventor： Hiroshi Asami ,  Hidetoshi Kusano ,  Yuki Nishitani ,  Ken Orui

IPC: H05K3/36

CPC classification number: H05K3/4694 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/0023 ,  H05K3/205 ,  H05K3/4617 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/09536 ,  H05K2201/09881 ,  H05K2201/09972 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.

Abstract translation: 本发明提供一种制造多层布线基板的方法，其可以以细间距保持导体图案的尺寸稳定性，从材料选择的角度解决对工艺的限制，并且进一步降低制造成本，并且 多层布线基板。 形成在由金属制成的支撑片和粘合剂层上的第二布线基板通过使用支撑片部分堆叠在第一布线基板的预定区域上。 在第二布线基板的层叠之后，最后蚀刻并去除支撑片。 第二布线基板仅堆叠在第一布线基板上需要多层的部分上，从而减少第二布线基板的结构材料的量。

公开(公告)号：US07415761B2

公开(公告)日：2008-08-26

申请号：US10356464

申请日：2003-02-03

Applicant: Naohiro Hirose ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

Inventor： Naohiro Hirose ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

IPC: H01K3/10

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Abstract translation: 通过激光束在树脂20中形成开口，从而形成通孔。 此时，通过进行蚀刻来降低导热率的铜箔22的厚度（3μm）被用作保形掩模。 因此，如果脉冲形激光束的照射次数减少，则可以在树脂20中形成开口部20a。 因此，可以防止形成层间绝缘树脂层的树脂20的底切的发生。 因此，可以提高通孔连接的可靠性。

公开(公告)号：US07407883B2

公开(公告)日：2008-08-05

申请号：US11529027

申请日：2006-09-28

Applicant: Govindarajan Natarajan ,  Raschid J Bezama

Inventor： Govindarajan Natarajan ,  Raschid J Bezama

IPC: H01L21/44

CPC classification number: H05K1/0265 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K2201/09881 ,  H01L2924/00

Abstract: An electronic package and method for forming such package that expands the current capability of lines and/or reducing line resistance for packages with a given feature dimension while relaxing feature tolerances. The methods and structures include electrical wirings having regions of larger wire cross-sectional areas in locations where the package must supply higher current distribution to the electronic devices and/or where signal lines need lower electrical resistance. These larger wire cross-sectional areas are vertically extended conductors applied to either the entire conductor or portions of the conductor.

公开(公告)号：US07383630B2

公开(公告)日：2008-06-10

申请号：US11166058

申请日：2005-06-24

Applicant: Yu-Nung Shen

Inventor： Yu-Nung Shen

IPC: H01K3/10 ,  H05K3/02

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/0002 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/246 ,  H05K3/28 ,  H05K3/388 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09881 ,  Y10T29/49135 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for making a circuit plate includes: forming first holes in an insulating layer; forming a conductive layer on the insulating layer such that a portion of the conductive layer fills the first holes; grinding the conductive layer such that the portion of the conductive layer remains in the first holes to form a pattern of conductive traces; forming a dielectric protective layer that covers the insulating layer and the conductive traces; forming a pattern of second holes in the protective layer such that a portion of each of the conductive traces is accessible through a respective one of the second holes; and forming conductive bumps that are respectively connected to the conductive traces.

Abstract translation: 制造电路板的方法包括：在绝缘层中形成第一孔; 在所述绝缘层上形成导电层，使得所述导电层的一部分填充所述第一孔; 研磨导电层，使得导电层的部分保留在第一孔中以形成导电迹线图案; 形成覆盖绝缘层和导电迹线的介电保护层; 在保护层中形成第二孔的图案，使得每个导电迹线的一部分可通过相应的一个第二孔接近; 以及形成分别连接到导电迹线的导电凸块。

公开(公告)号：US07288724B2

公开(公告)日：2007-10-30

申请号：US10403550

申请日：2003-03-31

Applicant: Hiroshi Asami ,  Hidetoshi Kusano ,  Yuji Nishitani ,  Ken Orui

Inventor： Hiroshi Asami ,  Hidetoshi Kusano ,  Yuji Nishitani ,  Ken Orui

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14

CPC classification number: H05K3/4694 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/0023 ,  H05K3/205 ,  H05K3/4617 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/09536 ,  H05K2201/09881 ,  H05K2201/09972 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiling substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.

Abstract translation: 制造可以以细间距保持导体图案的尺寸稳定性的多层布线基板的方法从材料选择的角度解决了对工艺的限制，并且进一步降低了制造成本，以及多层布线基板。 形成在由金属制成的支撑片和粘合剂层上的第二布线基板通过使用支撑片部分堆叠在第一布线基板的预定区域上。 在第二布线基板的层叠之后，最后蚀刻并去除支撑片。 第二卷绕基板仅叠层在第一布线基板上的多层的部分上，从而减少第二布线基板的结构材料的量。

公开(公告)号：US20070194456A1

公开(公告)日：2007-08-23

申请号：US11360200

申请日：2006-02-23

Applicant: Charles Cohn

Inventor： Charles Cohn

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/4985 ,  H01L2224/16225 ,  H05K1/0204 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/064 ,  H05K3/202 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09881 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0376 ,  Y02P70/611

Abstract: A circuit substrate for attachment to an integrated circuit chip comprises an electrical trace, a mounting pad and a dielectric layer. The mounting pad has a first surface, one or more sidewalls and a second surface. The first surface is attached to the electrical trace. The dielectric layer substantially covers the one or more sidewalls of the mounting pad and has an uppermost surface that is substantially coplanar with the second surface of the mounting pad.

Abstract translation: 用于附接到集成电路芯片的电路基板包括电迹线，安装焊盘和介电层。 安装垫具有第一表面，一个或多个侧壁和第二表面。 第一个表面附着在电气痕迹上。 电介质层基本上覆盖安装焊盘的一个或多个侧壁，并且具有与安装焊盘的第二表面基本共面的最上表面。

公开(公告)号：US20070171621A1

公开(公告)日：2007-07-26

申请号：US11626379

申请日：2007-01-24

Applicant: Tsung-Yuan Chen

Inventor： Tsung-Yuan Chen

IPC: H05K7/00 ,  H05K3/10

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/09881 ,  H05K2203/0361 ,  H05K2203/0723 ,  Y10T29/49155 ,  Y10T156/1028

Abstract: A process for fabricating a circuit board with an embedded passive component is provided. First, an electrode-patterned layer having electrodes is formed on a surface of a conductive layer. Then, a passive component material is filled in the intervals between the electrodes. Then, the conductive layer and the electrode-patterned layer are laminated to a dielectric layer, wherein the electrode-patterned layer is embedded in the dielectric layer. Next, the conductive layer is patterned to form a circuit layer.

Abstract translation: 提供了一种用于制造具有嵌入式无源元件的电路板的工艺。 首先，在导电层的表面上形成具有电极的电极图案层。 然后，在电极之间的间隔中填充无源元件材料。 然后，将导电层和电极图案层层压到电介质层，其中电极图案层被嵌入在电介质层中。 接下来，对导电层进行图案化以形成电路层。

公开(公告)号：US20070111380A1

公开(公告)日：2007-05-17

申请号：US11598141

申请日：2006-11-13

Applicant: Suk-Hyeon Cho ,  Chang-Sup Ryu ,  Han-Seo Cho ,  Han Kim

Inventor： Suk-Hyeon Cho ,  Chang-Sup Ryu ,  Han-Seo Cho ,  Han Kim

IPC: H01L21/00

CPC classification number: H05K1/162 ,  H01F17/0033 ,  H01F41/046 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09881 ,  H05K2203/0361

Abstract: A method of fabricating a printed circuit board having embedded components is disclosed. The method of fabricating a printed circuit board having embedded components according to an embodiment of the present invention comprises stacking a first conductive layer and a second conductive layer on a substrate in order, forming a hole in the second conductive layer and filling with dielectric material, stacking a third conductive layer on the second conductive layer and removing portions to form an upper electrode located on the dielectric material and a pad electrically connected with the first conductive layer, and stacking an insulation layer on the third conductive layer and forming a via hole and an outer layer circuit electrically connected with the upper electrode and the pad, so that it is easy to process the dielectric material to have a uniform thickness, and the capacitor and the resistor can be implemented simultaneously.

Abstract translation: 公开了一种制造具有嵌入式部件的印刷电路板的方法。 根据本发明的实施例的制造具有嵌入部件的印刷电路板的方法包括在基板上层叠第一导电层和第二导电层，以在第二导电层中形成孔并填充电介质材料， 在所述第二导电层上堆叠第三导电层并去除部分以形成位于所述电介质材料上的上电极和与所述第一导电层电连接的焊盘，以及在所述第三导电层上堆叠绝缘层并形成通孔，以及 与上电极和焊盘电连接的外层电路，使得容易将电介质材料加工成具有均匀的厚度，并且可以同时实现电容器和电阻器。