公开(公告)号：US10079222B2

公开(公告)日：2018-09-18

申请号：US15353721

申请日：2016-11-16

Applicant: Powertech Technology Inc.

Inventor： Chien-Wei Chou ,  Yong-Cheng Chuang

IPC: H01L23/48 ,  H01L25/065 ,  H05K1/18 ,  H05K1/11 ,  H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L25/0657 ,  H01L21/4821 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0203 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y02P70/611 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2924/014

Abstract: A POP structure includes a circuit board, a bottom package structure, a top package structure, and a metal frame structure. The circuit board has a plurality of signal pads and dummy pads. The dummy pads surround the signal pads. The bottom package structure is disposed over the circuit board. The bottom package structure is electrically connected to the signal pads. The top package structure is disposed over the bottom package structure. The top package structure is electrically connected to the bottom package structure. The metal frame structure includes a body and a plurality of terminal pins. The body is located between the top package structure and the bottom package structure. The terminal pins extend outward from an edge of the top package structure to connect the top package structure and the dummy pads of the circuit board.

公开(公告)号：US20180248092A1

公开(公告)日：2018-08-30

申请号：US15900685

申请日：2018-02-20

Applicant: Jen-You Liang

Inventor： Jen-You Liang

IPC: H01L33/62 ,  H01L33/60 ,  H05K1/03 ,  H05K1/18

CPC classification number: H01L33/62 ,  H01L33/486 ,  H01L33/60 ,  H05K1/03 ,  H05K1/05 ,  H05K1/181 ,  H05K3/0052 ,  H05K2201/09745 ,  H05K2201/10106 ,  H05K2201/10227 ,  H05K2201/10522 ,  H05K2201/1053

Abstract: A light sensor lead frame substrate may comprise a plurality of lead frame substrates formed on a metal substrate through a series of processing including chemical etching, plasma etching and stamping. The lead frame substrates are connected through a plurality of connecting sections, and each of the lead frame substrates is connected to the metal substrate through the connecting section. Each of the connecting sections has two pre-cut sections respectively formed at two ends of the connecting section. After molding, the lead frame substrates are configured to pass through a series of processing including electroplating, injection and desmear to enable each of the lead frame substrates to have a first insulating layer, a reflector cup and a second insulating layer, and with the pre-cut sections, the connecting sections are adapted to be easily washed down by a punch in the punching process.

公开(公告)号：US10002825B2

公开(公告)日：2018-06-19

申请号：US15625083

申请日：2017-06-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/538 ,  H05K3/00 ,  H01L21/683 ,  H05K3/32 ,  H05K3/10 ,  H01L23/00 ,  H05K1/02 ,  H05K3/46 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US09913375B2

公开(公告)日：2018-03-06

申请号：US15276073

申请日：2016-09-26

Applicant: International Business Machines Corporation

Inventor： Ai Kiar Ang ,  Michael Lauri

IPC: H01L23/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32 ,  H05K3/34 ,  H05K1/14 ,  H01L23/495 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H05K1/03

CPC classification number: H05K1/11 ,  H01L21/4839 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49565 ,  H01L23/49575 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/1029 ,  H01L2924/181 ,  H05K1/0313 ,  H05K1/144 ,  H05K1/18 ,  H05K1/181 ,  H05K3/328 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3426 ,  H05K2201/10015 ,  H05K2201/10227 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10962 ,  Y02P70/613 ,  H01L2924/00012

Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

公开(公告)号：US09874316B2

公开(公告)日：2018-01-23

申请号：US14370345

申请日：2012-12-21

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Jianghong Yu ,  Giovanni Cennini

IPC: F21S4/00 ,  F21K99/00 ,  F21K9/00 ,  F21V29/00 ,  F21K9/20 ,  H05K1/02 ,  H05K3/00 ,  H01L33/64 ,  F21Y115/10

CPC classification number: F21K9/20 ,  F21K9/00 ,  F21V29/70 ,  F21Y2115/10 ,  H01L33/641 ,  H01L2224/48137 ,  H05K1/0209 ,  H05K3/0061 ,  H05K2201/10106 ,  H05K2201/1053

Abstract: A lighting assembly, a light source and a luminaire are provided. The lighting assembly 100 comprises a primary thermal layer 112, a plurality of Lighting Emitting Diode assemblies 106 and a plurality of wires 102. The primary thermal layer 112 is of a thermally conductive material. The wires 102 are electrically coupled between electrodes 108, 114 of at least two different Light Emitting Diode assemblies 106. The Light Emitting Diode assemblies 106 comprise a sub-mount 110, a first and a second metal electrode 108, 114 and a Light Emitting Diode die 116. The sub-mount 110 is of a thermally conductive and electrically insulating ceramic. The sub-mount 110 has a first side which is thermally coupled to the primary thermal layer 112 and has a second side being opposite the first side. The first and the second metal electrode 108, 114 are arranged at the second side of the sub-mount 10. The Light Emitting Diode die 116 is electrically and thermally coupled with an anode of the Light Emitting Diode to the first metal electrode and with a cathode of the Light Emitting Diode to the second metal electrode.

公开(公告)号：US09844139B2

公开(公告)日：2017-12-12

申请号：US14211127

申请日：2014-03-14

Applicant: Indiana Integrated Circuits, LLC

Inventor： Jason M. Kulick ,  Tian Lu

IPC: H05K3/34 ,  H05K1/18

CPC classification number: H05K1/18 ,  H05K1/181 ,  H05K3/34 ,  H05K2201/1053 ,  Y02P70/611 ,  Y10T29/49128

Abstract: Apparatuses and methods related to the field of microchip assembly and handling, in particular to devices and methods for assembling and handling microchips manufactured with solid edge-to-edge interconnects, such as Quilt Packaging® interconnect technology. Specialized assembly tools are configured to pick up one or more microchips, place the microchips in a specified location aligned to a substrate, package, or another microchip, and facilitate electrical contact through one of a variety of approaches, including solder reflow. This specialized assembly tooling performs heating functions to reflow solder to establish electrical and mechanical interconnections between multiple microchips. Additionally, the interconnected microchips may be arranged in an arbitrarily large array.

公开(公告)号：US20170352615A1

公开(公告)日：2017-12-07

申请号：US15625083

申请日：2017-06-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L23/538 ,  H05K3/32 ,  H05K3/00 ,  H05K1/18 ,  H01L21/683 ,  H05K3/46 ,  H01L23/00 ,  H01L23/31 ,  H05K1/02 ,  H05K3/10

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US09721880B2

公开(公告)日：2017-08-01

申请号：US14969940

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Sanka Ganesan ,  Shawna M. Liff ,  Yikang Deng ,  Debendra Mallik

IPC: H01L23/12 ,  H01L21/00 ,  H05K7/10 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H05K1/18 ,  H05K1/03 ,  H05K3/34 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14135 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15321 ,  H01L2924/3511 ,  H05K1/03 ,  H05K1/18 ,  H05K1/181 ,  H05K3/34 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01028

Abstract: Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.

公开(公告)号：US09698123B2

公开(公告)日：2017-07-04

申请号：US13235166

申请日：2011-09-16

Applicant: Arifur Rahman ,  Jon M. Long ,  Yuanlin Xie

Inventor： Arifur Rahman ,  Jon M. Long ,  Yuanlin Xie

IPC: H01L25/065 ,  H01L23/00 ,  H05K3/46 ,  H05K1/14

CPC classification number: H01L25/0652 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H05K1/141 ,  H05K3/4697 ,  H05K2201/1053 ,  H01L2924/014 ,  H01L2924/00

Abstract: An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.

公开(公告)号：US09698083B2

公开(公告)日：2017-07-04

申请号：US14727554

申请日：2015-06-01

Applicant: Infineon Technologies AG

Inventor： Alfred Swain Hong Yeo

IPC: H01R9/00 ,  H01L23/495 ,  H01L21/56 ,  H01L25/16 ,  H05K1/18 ,  H05K3/34 ,  H01L23/31

CPC classification number: H01L23/49531 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49555 ,  H01L23/49589 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H05K1/18 ,  H05K3/3426 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10689 ,  H05K2201/10765 ,  H05K2201/10772 ,  H05K2201/10962 ,  Y02P70/613 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: An electronic device comprising a package comprising an encapsulated electronic chip, at least one at least partially exposed electrically conductive carrier lead for mounting the package on and electrically connecting the electronic chip to a carrier, and at least one at least partially exposed electrically conductive connection lead, and an electronic member stacked with the package so as to be mounted on and electrically connected to the package by the at least one connection lead.