公开(公告)号：US20150163916A1

公开(公告)日：2015-06-11

申请号：US14452785

申请日：2014-08-06

Applicant: Mitsubishi Electric Corporation

Inventor： Taichi OBARA ,  Rei YONEYAMA ,  Takami OTSUKI ,  Eiju SHITAMA

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3735 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L2224/32225 ,  H01L2924/19105 ,  H05K1/11 ,  H05K1/111 ,  H05K1/186 ,  H05K1/188 ,  H05K3/3442 ,  H05K2201/09072 ,  H05K2201/09745 ,  H05K2201/10 ,  H05K2201/10174 ,  H05K2201/1059 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K2201/10674 ,  H05K2201/10689 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic component mounting device includes an insulating substrate having a metal pattern formed thereon and a MELF electronic component. The MELF electronic component is fitted into a first receiving portion configured with the metal pattern and the insulating substrate exposed from a lacking portion of the metal pattern. The electronic component mounting device further includes a conductive member formed between the MELF electronic component and the metal pattern, and the conductive member is not formed between the MELF electronic component and the insulating substrate.

Abstract translation: 电子部件安装装置包括其上形成有金属图案的绝缘基板和MELF电子部件。 MELF电子部件装配到由金属图案构成的第一接收部分和从金属图案的缺少部分露出的绝缘基板。 电子部件安装装置还包括形成在MELF电子部件和金属图案之间的导电部件，并且在MELF电子部件和绝缘基板之间不形成导电部件。

公开(公告)号：US20150156881A1

公开(公告)日：2015-06-04

申请号：US14555856

申请日：2014-11-28

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU ,  Yuichi NAKAMURA ,  Tsuyoshi YAMAGUCHI

IPC: H05K1/18 ,  H05K3/10 ,  H05K3/42 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/06152 ,  H01L2224/06153 ,  H01L2224/12105 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15313 ,  H05K1/181 ,  H05K1/185 ,  H05K3/30 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/4913

Abstract: A substrate with a built-in electronic component includes multiple resin insulating layers including first, second, third and fourth insulating layers, multiple conductor layers including a first wiring layer including a first pad, a second wiring layer including a second pad, and a third wiring layer including third and fourth pads, multiple via conductors including a first via connecting the first and second pads through the second insulating layer, a second via connecting the second and third pads through the third and fourth insulating layers, and a third via connected to the fourth pad through the fourth insulating layer, and an electronic component positioned a cavity through the second and third insulating layers such that the third via is connecting terminal of the component and fourth pad. The second and third vias have filled plating filling opening portions through the third and fourth insulating layers and through the fourth insulating layer.

Abstract translation: 具有内置电子部件的基板包括包括第一，第二，第三和第四绝缘层的多个树脂绝缘层，多个导体层，包括包括第一焊盘的第一布线层，包括第二焊盘的第二布线层和第三焊盘的第三布线层 包括第三和第四焊盘的布线层，多个通孔导体，包括通过第二绝缘层连接第一和第二焊盘的第一通孔，通过第三和第四绝缘层连接第二和第三焊盘的第二通孔，以及连接到 通过第四绝缘层的第四焊盘和通过第二和第三绝缘层定位空腔的电子部件，使得第三通孔是部件和第四焊盘的连接端子。 第二和第三通孔已经通过第三绝缘层和第四绝缘层填充电镀填充开口部分并穿过第四绝缘层。

公开(公告)号：US20150156880A1

公开(公告)日：2015-06-04

申请号：US14555840

申请日：2014-11-28

Applicant: IBIDEN CO., LTD.

Inventor： Tomoya DAIZO

IPC: H05K1/18 ,  B23K26/40 ,  H05K3/06 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K1/02 ,  H05K1/03 ,  B23K26/38 ,  H05K3/02

CPC classification number: H05K1/183 ,  B23K26/364 ,  B23K26/40 ,  B23K2101/35 ,  B23K2101/42 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/09127 ,  H05K2201/10674 ,  H01L2924/014

Abstract: A printed wiring board includes a core substrate, a first build-up layer formed on first surface of the substrate and having a recess formed to accommodate an electronic component, a second build-up layer formed on second surface of the substrate, and multiple pads including first pads on the first layer, second pads on the second layer, and third pads in bottom surface of the recess. The first and second layers have interlayer insulating layers, the insulating layers in interior portion of the first layer between the substrate and the bottom surface of the recess has number of insulating layers equal to number of insulating layers in the second layer, and the insulating layers in exterior portion of the first layer between the core substrate and the surface of the first layer has number of insulating layers greater than number of insulating layers in the second layer.

Abstract translation: 印刷电路板包括芯基板，形成在基板的第一表面上并具有形成为容纳电子部件的凹部的第一累积层，形成在基板的第二表面上的第二累积层，以及多个焊盘 包括第一层上的第一焊盘，第二层上的第二焊盘和凹部的底表面中的第三焊盘。 第一层和第二层具有层间绝缘层，衬底与凹部底面之间的第一层的内部部分中的绝缘层具有与第二层中的绝缘层数相等的绝缘层数，绝缘层 在核心基板和第一层的表面之间的第一层的外部部分具有大于第二层中绝缘层数量的绝缘层数量。

公开(公告)号：US09049791B2

公开(公告)日：2015-06-02

申请号：US13912652

申请日：2013-06-07

Applicant: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/02 ,  H01L23/00 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15788 ,  H05K1/115 ,  H05K3/0082 ,  H05K3/108 ,  H05K3/282 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of attaching a chip to the substrate with an outer layer consisting of via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method consisting of optionally removing an organic varnish, positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract translation: 一种将芯片附着到具有外部层的方法，所述外层由嵌入在电介质如焊料掩模中的通孔柱构成，通孔的端部与所述电介质齐平，所述方法包括任选地除去有机清漆，将芯片定位 具有以与通孔支柱的暴露端接触的焊料凸块端接的腿，并施加热量以熔化焊料凸块并用焊料润湿通孔的端部。

公开(公告)号：US09040347B2

公开(公告)日：2015-05-26

申请号：US13984889

申请日：2012-03-22

Applicant: Yujuan Tao ,  Lei Shi

Inventor： Yujuan Tao ,  Lei Shi

IPC: H01L21/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/50

CPC classification number: H01L23/49822 ,  H01L21/50 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/23 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer.

Abstract translation: 扇出式高密度封装方法包括提供封装衬底，在封装衬底上形成剥离膜，以及在剥离膜上形成第一保护层和在第一保护层上形成预先设计的光刻图案孔。 该方法还包括在第一保护层的表面上和在光刻图案开口中形成金属再分配层，在第一保护层上形成第二保护层，并部分地暴露金属再分布层，并且形成至少一个封装层 第二保护层。 至少一个封装层中的每一个包括依次形成的直的安装层，密封剂层和布线层，并且封装层通过布线层连接金属再分配层。 此外，该方法包括在至少一个封装层的顶部上形成至少一个顶层封装层，去除封装衬底和剥离膜以暴露第一保护层中的金属再分配层，并将金属焊球放置在 暴露的金属再分配层。

公开(公告)号：US20150121692A1

公开(公告)日：2015-05-07

申请号：US14391489

申请日：2013-03-15

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO. LTD

Inventor： Hideki Eifuku

IPC: H05K3/34

CPC classification number: H05K3/341 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/743 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/75272 ,  H01L2224/75301 ,  H01L2224/755 ,  H01L2224/75611 ,  H01L2224/7565 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/83862 ,  H01L2224/92143 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15787 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/53174 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/01049 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided is an electronic component mounting method including the steps of: placing an electronic component having a primary surface on which a first electrode is formed, on a circuit member having a primary surface on which a second electrode corresponding to the first electrode is formed, with solder and a bonding material including a thermosetting resin interposed between the first and second electrodes; subjecting the thermosetting resin to a first heating at a temperature lower than the melting point of the solder and thus causing the resin to cure, while pressing the electronic component against the circuit member, and then releasing pressure applied for the pressing; and subjecting the solder interposed between the first and second electrodes to a second heating with the pressure released, and thus melting the solder to electrically connect the first and second electrodes.

Abstract translation: 提供一种电子部件安装方法，包括以下步骤：将具有形成有第一电极的主表面的电子部件放置在具有与形成有第一电极的第二电极相对应的主表面的电路部件上， 焊料和包含置于第一和第二电极之间的热固性树脂的接合材料; 在低于焊料的熔点的温度下对热固性树脂进行第一次加热，从而使树脂固化，同时将电子部件压靠在电路部件上，然后释放施加的压力; 并且将放置在第一和第二电极之间的焊料进行第二加热，释放压力，从而使焊料熔化以电连接第一和第二电极。

公开(公告)号：US09023464B2

公开(公告)日：2015-05-05

申请号：US12838625

申请日：2010-07-19

Applicant: Yasushi Akutsu ,  Tomoyuki Ishimatsu ,  Koichi Miyauchi

Inventor： Yasushi Akutsu ,  Tomoyuki Ishimatsu ,  Koichi Miyauchi

IPC: H01R4/04 ,  C09J7/00 ,  H01L23/00 ,  H05K3/32 ,  C08K3/00 ,  C08K3/08 ,  C08K9/02 ,  H05K1/03

CPC classification number: C09J7/00 ,  C08K3/017 ,  C08K3/08 ,  C08K9/02 ,  C09J7/10 ,  C09J2201/134 ,  C09J2201/36 ,  C09J2205/102 ,  C09J2433/00 ,  C09J2463/00 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/15788 ,  H01R4/04 ,  H05K1/0346 ,  H05K3/323 ,  H05K2201/0154 ,  H05K2201/10674 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T428/25 ,  Y10T428/31511 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/0401

Abstract: A connecting film which electrically connects a first circuit member with a second circuit member having a nitrogen atom-containing film on a surface thereof facing the first circuit member, the connecting film including a first layer which is to be located at the first circuit member side, and a second layer which is to be located at the second circuit member side, wherein the first layer contains a cationic curing agent and an epoxy resin, and the second layer contains a radical curing agent, an acrylic resin and an epoxy compound, wherein one of the first layer and the second layer is a conductive particle-containing organic resin layer, and the other layer is an insulating organic resin layer containing no conductive particles, and wherein the minimum melt viscosity of the conductive particle-containing organic resin layer is ten times or more greater than that of the insulating organic resin layer.

Abstract translation: 一种连接膜，其将第一电路部件与具有含氮原子的膜的第二电路部件的面对第一电路部件的表面电连接，所述连接膜包括位于第一电路部件侧的第一层 以及位于第二电路部件侧的第二层，其中第一层含有阳离子固化剂和环氧树脂，第二层含有自由基固化剂，丙烯酸树脂和环氧化合物，其中， 第一层和第二层之一是含导电粒子的有机树脂层，另一层是不含导电性粒子的绝缘性有机树脂层，其中，导电性粒子的有机树脂层的最小熔融粘度为 是绝缘性有机树脂层的10倍以上。

公开(公告)号：US09018743B2

公开(公告)日：2015-04-28

申请号：US13566082

申请日：2012-08-03

Applicant: Min Jae Lee ,  You Shin Chung ,  Hoon Jung

Inventor： Min Jae Lee ,  You Shin Chung ,  Hoon Jung

IPC: H01L23/495 ,  H01L23/00 ,  H05K3/34 ,  H05K3/30 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1412 ,  H01L2224/14133 ,  H01L2224/16105 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/00014 ,  H05K3/303 ,  H05K3/3452 ,  H05K2201/09418 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.

Abstract translation: 提供一种半导体器件，其中当半导体管芯附接到电路板时，可以防止或显着减小半导体管芯和衬底（例如电路板）之间的偏移。 在非限制性示例中，半导体器件包括：包括至少一个凸块的半导体管芯; 以及电路板，其包括至少一个电路图案，所述凸块电连接到所述电路图案。 在非限制性示例中，电路板包括：绝缘层，包括中心区域和围绕中心区域的周边区域; 形成在所述绝缘层的中心区域中的多个中心电路图案; 以及形成在绝缘层的周边区域中的多个外围电路图案。 中心电路图案可以形成为比以Z字形图案形成的外围电路图形更宽，和/或可以形成为交叉形状。

公开(公告)号：US09018538B2

公开(公告)日：2015-04-28

申请号：US13892416

申请日：2013-05-13

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Kotaro Kodani ,  Junichi Nakamura

IPC: H05K1/16 ,  H05K1/18 ,  H05K1/11 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H05K3/40 ,  H01L21/56 ,  H05K3/20 ,  H05K3/46

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2221/68359 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15174 ,  H05K1/09 ,  H05K1/111 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/10242 ,  H05K2201/10674 ,  H05K2203/0376 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of making a wiring substrate includes forming a first metal layer on a surface of a support member, the first metal layer having at least one columnar through hole that exposes the surface of the support member, forming a columnar metal layer that fills the columnar through hole, forming an insulating layer on the columnar metal layer and on the first metal layer, forming an interconnection layer on a first surface of the insulating layer such that the interconnection layer is electrically connected to the columnar metal layer through the insulating layer, and forming a protruding part including at least part of the columnar metal layer by removing at least the support member and the first metal layer, the protruding part protruding from a second surface of the insulating layer opposite the first surface and serving as at least part of a connection terminal of the wiring substrate.

Abstract translation: 制造布线基板的方法包括在支撑构件的表面上形成第一金属层，所述第一金属层具有至少一个柱状通孔，所述柱状通孔暴露所述支撑构件的表面，形成填充柱状的柱状金属层 在所述柱状金属层和所述第一金属层上形成绝缘层，在所述绝缘层的第一表面上形成互连层，使得所述互连层通过所述绝缘层与所述柱状金属层电连接，以及 通过至少移除所述支撑构件和所述第一金属层来形成包括所述柱状金属层的至少一部分的突出部分，所述突出部分从所述绝缘层的与所述第一表面相对的第二表面突出并且用作所述第一金属层的至少一部分 接线基板的连接端子。

公开(公告)号：US20150103494A1

公开(公告)日：2015-04-16

申请号：US14513436

申请日：2014-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee-jeong Kim ,  Eun-Chul AHN ,  Yong-Kwan LEE

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/09

CPC classification number: H05K3/24 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/18161 ,  H05K2201/10674 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Printed circuit boards are provided. The printed circuit board includes an insulation layer, an interconnection portion and a metal layer. The insulation layer has a flat plate shape and includes a top surface and a bottom surface. The interconnection portion is disposed on at least one of the top and bottom surfaces of the insulation layer. The interconnection portion includes a plurality of interconnection patterns. The metal layer covers the plurality of interconnection patterns of the interconnection portion. Related semiconductor packages are also provided.

Abstract translation: 提供印刷电路板。 印刷电路板包括绝缘层，互连部分和金属层。 绝缘层具有平板形状并且包括顶表面和底表面。 互连部分设置在绝缘层的顶表面和底表面中的至少一个上。 互连部分包括多个互连图案。 金属层覆盖互连部分的多个互连图案。 还提供了相关的半导体封装。