公开(公告)号：US6024275A

公开(公告)日：2000-02-15

申请号：US97856

申请日：1998-06-16

Applicant: Hem P. Takiar

Inventor： Hem P. Takiar

IPC: B22C9/20 ,  H01L21/48 ,  H01L21/60 ,  H01L21/68 ,  H05K3/34 ,  B23K31/02 ,  B23K35/12

CPC classification number: B22C9/20 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H05K3/3484 ,  H01L2224/11003 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2201/035 ,  H05K2201/0379 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K3/3463

Abstract: A method of producing an array of interconnecting contacts for an integrated circuit package, such as a flip chip integrated circuit, and connecting the array of interconnecting contacts to the package utilizes a mold to form the array and attach the array to the package. The method may also be used to interconnect two integrated circuit die. The mold defines a desired shape and relative position for a plurality of interconnecting contacts which make up the array of interconnecting contacts. The array of interconnecting contacts are molded by filling the mold with a desired contact forming material such as solder paste. The mold containing the molded array of interconnecting contacts is positioned adjacent to the integrated circuit package such that each interconnecting contact is positioned adjacent to a corresponding contact pad of the integrated circuit package. And finally, the molded interconnecting contacts are attached to their corresponding contact pads of the integrated circuit package. In the case in which solder paste is utilized as the molding material, the solder is reflowed to attach the array to the package.

Abstract translation: 制造用于集成电路封装（例如倒装芯片集成电路）并且将互连触点阵列连接到封装的互连触点阵列的方法利用模具形成阵列并将阵列附接到封装。 该方法也可用于互连两个集成电路管芯。 模具限定了构成互连触点阵列的多个互连触头的期望形状和相对位置。 通过用所需的接触形成材料（例如焊膏）填充模具来模制互连触点阵列。 包含互连触点的模制阵列的模具被定位成与集成电路封装件相邻，使得每个互连触点定位成与集成电路封装件的相应接触焊盘相邻。 最后，模制的互连触点附接到其对应的集成电路封装的接触焊盘。 在使用焊膏作为模塑材料的情况下，焊料被回流以将阵列附接到封装。

公开(公告)号：US5679008A

公开(公告)日：1997-10-21

申请号：US570386

申请日：1995-12-11

Applicant: Hisafumi Takahashi ,  Kouichi Uchiyama

Inventor： Hisafumi Takahashi ,  Kouichi Uchiyama

IPC: H01R9/05 ,  H01R13/512 ,  H05K1/11 ,  H05K1/14 ,  H01R9/09

CPC classification number: H01R9/0515 ,  H01R13/512 ,  H05K1/117 ,  H01R12/598 ,  H05K1/144 ,  H05K2201/0379 ,  H05K2201/0715 ,  H05K2201/09354 ,  H05K2201/10356

Abstract: An electrical connector 1 comprises a mediate circuit board assembly 4, a housing 2, and a plurality of contacts 3. The mediate circuit board assembly 4 has a plurality of signal paths, to which signal cables 5 are connected, and the housing 2 houses this mediate circuit board assembly 4. The contacts 3 are retained in the housing 2 and connected to the signal paths of the mediate circuit board assembly 4, which is housed in the housing 2. Two double-sided circuit boards, each having at least the signal paths formed on the front face and a grounding path formed on the rear face, constitute the mediate circuit board assembly 4 when these two double-sided circuit boards are abutted with each other, connecting the grounding paths of their rear faces.

Abstract translation: 电连接器1包括中介电路板组件4，壳体2和多个触点3.中间电路板组件4具有多个信号路径，信号电缆5连接到该多个信号路径，并且壳体2容纳该 介质电路板组件4.触点3保持在壳体2中并连接到容纳在壳体2中的中介电路板组件4的信号路径。两个双面电路板，每个至少具有信号 形成在前表面上的路径和形成在后表面上的接地路径构成了当这两个双面电路板彼此抵接时​​连接其后表面的接地路径的中间电路板组件4。

公开(公告)号：US5598036A

公开(公告)日：1997-01-28

申请号：US490855

申请日：1995-06-15

Applicant: Tony H. Ho

Inventor： Tony H. Ho

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K3/34 ,  H01L23/58 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L23/49816 ,  H05K3/3436 ,  H05K3/3463 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K2201/0379 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/0465 ,  Y02P70/613 ,  Y10T29/49222

Abstract: A semiconductor package, including semiconductor dies, a ball grid array, and a printed circuit board, is described. Said package has been designed with a view to minimizing its level of internal mechanical stress. This has been achieved through use of two sets of solder joints that have different melting points. The joints with the higher melting point are positioned in the region, on the ball grid array, where it is known that stress will be a maximum in the finished package. The lower melting point joints occupy the remaining positions on the underside of the ball grid array. Ball grid array and printed circuit board are attached to one another by heating at a temperature that is between the aforementioned two melting points.

Abstract translation: 描述了包括半导体管芯，球栅阵列和印刷电路板的半导体封装。 所述封装被设计为使其内部机械应力的水平最小化。 这是通过使用具有不同熔点的两组焊点实现的。 具有较高熔点的接头位于球栅阵列上的区域中，已知压力在成品包装中将是最大的。 低熔点接头占据球栅阵列下侧的剩余位置。 球栅阵列和印刷电路板通过在上述两个熔点之间的温度下加热而相互连接。

公开(公告)号：US5499442A

公开(公告)日：1996-03-19

申请号：US271732

申请日：1994-07-07

Applicant: Nakaba Nakamura ,  Makoto Kosaki

Inventor： Nakaba Nakamura ,  Makoto Kosaki

IPC: H01F17/00 ,  H01F41/04 ,  H01P3/08 ,  H01P9/00 ,  H01P11/00 ,  H03H7/34 ,  H05K1/02 ,  H05K1/03 ,  H05K1/14 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/46

CPC classification number: H05K3/4614 ,  H01P9/006 ,  H05K3/368 ,  H05K3/4629 ,  H05K1/0237 ,  H05K1/0248 ,  H05K1/0272 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/0379 ,  H05K2201/0715 ,  H05K3/328 ,  H05K3/3436 ,  Y10T29/49016 ,  Y10T29/49126 ,  Y10T29/49146

Abstract: A delay line device having first and second substrates. The first substrate has a signal line centrally formed on one of main surfaces of a ceramic substrate, bonding electrodes formed in a peripheral portion of the main surface and a ground electrode formed over substantially the entire region of the other main surface thereof. The second substrate has bonding electrodes formed on one of main surfaces of the ceramic substrate identical in thickness and material to the ceramic substrate and a ground electrode formed over substantially the entire region of the other main surface thereof. The delay line device is formed by superimposing the first and second substrates on one another so that the bonding electrodes of the first substrate face those of the second substrate and bonding the bonding electrodes of both substrates to one another. Such delay line devices can be manufactured using mother substrates and mother dummy substrates.

Abstract translation: 一种具有第一和第二基板的延迟线装置。 第一基板具有中心形成在陶瓷基板的一个主表面上的信号线，形成在主表面的周边部分的接合电极和在其另一个主表面的基本上整个区域上形成的接地电极。 第二基板具有形成在与陶瓷基板相同厚度的陶瓷基板的一个主表面上的接合电极和在其另一个主表面的基本上整个区域上形成的接地电极。 延迟线器件通过将第一和第二衬底彼此叠加而形成，使得第一衬底的接合电极面对第二衬底的接合电极并且将两个衬底的接合电极彼此接合。 这样的延迟线装置可以使用母基板和母模板进行制造。

公开(公告)号：US4803450A

公开(公告)日：1989-02-07

申请号：US134268

申请日：1987-12-14

Applicant: James F. Burgess ,  Homer H. Glascock, II ,  Harold F. Webster ,  Constantine A. Neugebauer ,  James A. Loughran

Inventor： James F. Burgess ,  Homer H. Glascock, II ,  Harold F. Webster ,  Constantine A. Neugebauer ,  James A. Loughran

IPC: H01P3/08 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  B23K31/02 ,  B32B9/06 ,  H05K3/36

CPC classification number: H01P3/088 ,  H05K3/462 ,  H05K3/4629 ,  H05K1/0237 ,  H05K1/0272 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0305 ,  H05K2201/0379 ,  H05K2201/096 ,  H05K3/38 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4641 ,  Y10S428/901 ,  Y10T29/49126

Abstract: Multilayer circuit boards composed primarily of silicon and containing buried ground planes and buried conducting runs are fabricated in one embodiment by positioning conductive patterns (12) on the surfaces of silicon substrates and melting a solder component of the conductive patterns (12) and allowing it to flow together with solder from the conductive patterns (12) on a stacked, adjacent silicon substrate (10). When the solder cools, a single conductive pathway (18) exists between adjacent silicon substrates (10) and bonds the adjacent substrates. If the substrates are coated with SiO.sub.2 (20), a multilayer structure with buried microwave strip lines (22) is formed in the bonding process. Alternatively, highly resistive silicon substrates (26) are used as a dielectric for microwave strip lines (24) on a top surface thereof and a conductive sheet (28) on the bottom surface thereof acts as a ground plane for microwave energy propagating along strip line (24).

Abstract translation: 在一个实施例中，通过将导电图案（12）定位在硅衬底的表面上并熔化导电图案（12）的焊料组件，并使其成为 与来自堆叠的相邻硅衬底（10）上的导电图案（12）的焊料一起流动。 当焊料冷却时，在相邻硅衬底（10）之间存在单个导电通路（18），并且将相邻衬底粘合。 如果衬底被涂覆有SiO 2（20），则在接合过程中形成具有埋入的微波带状线（22）的多层结构。 或者，高电阻硅衬底（26）用作其顶表面上的微波带线（24）的电介质，并且其底表面上的导电片（28）用作沿着带状线传播的微波能量的接地面 （24）。

公开(公告)号：US4685210A

公开(公告)日：1987-08-11

申请号：US719560

申请日：1985-03-13

Applicant: Michael M. King ,  Helen J. Walter

Inventor： Michael M. King ,  Helen J. Walter

IPC: H01Q1/38 ,  H05K1/02 ,  H05K3/00 ,  H05K3/32 ,  H05K3/36 ,  H05K3/46

CPC classification number: H05K3/462 ,  H01Q1/38 ,  H05K3/368 ,  H05K1/0237 ,  H05K1/0272 ,  H05K2201/015 ,  H05K2201/0379 ,  H05K2201/0715 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0278 ,  H05K3/0094 ,  H05K3/328 ,  H05K3/4623 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: An electrically and mechanically sound conductive bond between layers of a multi-layer plated through hole circuit board is produced by depositing a layer of noble metal over the surfaces to be joined, juxtaposing the noble metal coated layers and subjecting them to a combination of pressure and heat for a sufficient period of time. Excellent results have been obtained in a multi-layer circuit board for a microstrip microwave antenna with 0.002 inch thick polished silver layers at bonding pressures of 490 to 575 psi and temperatures of 560 to 580 degrees F. for time periods of 20 to 30 minutes.

Abstract translation: 在多层电镀通孔电路板的层之间通过在待接合的表面上沉积贵金属层而制成电气和机械上的导电结合，并且并列贵金属涂覆层并使它们与压力和 加热一段足够的时间。 在具有0.002英寸厚的抛光银层的微带天线的多层电路板中，在490至575psi的接合压力和560至580华氏度的温度为20至30分钟的时间段内已经获得了优异的结果。

公开(公告)号：US3594493A

公开(公告)日：1971-07-20

申请号：US3594493D

申请日：1969-10-02

Applicant: ELLIOTT BROS

Inventor： KAUFFMAN ALAN MICHAEL ,  BOND JAMES

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/18 ,  H05K3/28 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46 ,  H05K1/18 ,  H05K3/36

CPC classification number: H05K3/284 ,  H05K1/113 ,  H05K3/002 ,  H05K3/181 ,  H05K3/32 ,  H05K3/4007 ,  H05K3/4084 ,  H05K3/4092 ,  H05K3/4611 ,  H05K3/4644 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/096 ,  H05K2201/10689 ,  H05K2201/10977 ,  H05K2203/025 ,  H05K2203/063 ,  H05K2203/1316 ,  H05K2203/1461 ,  H05K2203/1469

Abstract: A multilayer printed circuit assembly has connections between the layers formed by extending a printed circuit conductor from each layer through a number of aligned holes in the different layers to the outer surface of the assembly where the end faces of the conductors terminate in the same plane. A plated layer then interconnects the end faces. Component leads may also extend through holes to the connection plane. The assembly is potted in stages.

公开(公告)号：US12063750B2

公开(公告)日：2024-08-13

申请号：US17979150

申请日：2022-11-02

Applicant: Avary Holding (Shenzhen) Co., Limited. ,  QING DING PRECISION ELECTRONICS (HUAIAN) CO.,LTD

Inventor： Ying-Qiu Zheng ,  Chao Peng ,  Xian-Qin Hu

IPC: H05K1/02 ,  H05K1/05 ,  H05K1/09 ,  H05K3/06 ,  H05K3/24 ,  H05K3/28 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/246 ,  H05K1/095 ,  H05K3/067 ,  H05K3/4069 ,  H05K3/4664 ,  H05K3/28 ,  H05K2201/0347 ,  H05K2201/0379 ,  H05K2203/0514 ,  H05K2203/0723

Abstract: A method for manufacturing a circuit board with narrow conductive traces and narrow spaces between traces includes a base layer and two first wiring layers disposed on opposite surfaces of the base layer. Each first wiring layer includes a first bottom wiring and a first electroplated copper wiring. The first bottom wiring is formed on the base layer. The first bottom wiring includes a first end facing the base layer, a second end opposite to the first end, and a first sidewall connecting the first end and the second end. The first electroplated copper wiring covers the second end and the first sidewall of the first bottom wiring.

公开(公告)号：US20240179829A1

公开(公告)日：2024-05-30

申请号：US18095318

申请日：2023-01-10

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Chun Hung KUO

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0204 ,  H05K1/024 ,  H05K3/4673 ,  H05K3/4679 ,  H05K2201/0191 ,  H05K2201/0379 ,  H05K2203/0415

Abstract: A circuit board structure includes a build-up structure, a graphene layer disposed on the build-up structure, and at least one conductive pillar disposed on the graphene layer, the graphene layer includes an oxidized area not covered by the at least one conductive pillar and a non-oxidized area covered by the at least one conductive pillar, and the at least one conductive pillar is electrically connected to the build-up structure via the non-oxidized area.

公开(公告)号：US11908768B2

公开(公告)日：2024-02-20

申请号：US17671635

申请日：2022-02-15

Applicant: MITSUBISHI MATERIALS CORPORATION

Inventor： Ryohei Yumoto ,  Tomoya Oohiraki ,  Takeshi Kitahara ,  Yoshiyuki Nagatomo

IPC: H05K1/09 ,  H05K1/18 ,  H05K3/22 ,  H01L21/52 ,  H01L23/12 ,  H01L23/367 ,  H01L23/473 ,  H01L23/373 ,  H01L21/48 ,  H05K3/00 ,  H05K3/02

CPC classification number: H01L23/3735 ,  H01L21/4857 ,  H05K1/09 ,  H05K3/0097 ,  H05K3/022 ,  H05K3/0052 ,  H05K2201/0341 ,  H05K2201/0379 ,  H05K2203/068

Abstract: Forming aluminum circuit layers forming an aluminum circuit layers on one surface of a ceramic substrate and forming copper circuit layers are included. The copper circuit layers are formed by laminating copper boards for the circuit layers on the respective aluminum circuit layers, arranging the laminate between a pair of support boards having a convex curved surface at least on one surface so as to face to each other, moving the support boards in a facing direction to press the laminate in a lamination direction, and heating in this pressing state so that the copper boards for the circuit layers are bonded on the aluminum circuit layers respectively by solid phase diffusion. In the step of forming the copper circuit layers, the support boards are arranged so that either one of the convex curved surface is in contact with the adjacent copper boards for the circuit layers in the laminate.