公开(公告)号：US09433109B2

公开(公告)日：2016-08-30

申请号：US14308853

申请日：2014-06-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kentaro Kaneko ,  Katsuya Fukase

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  H05K3/40 ,  H05K3/34 ,  H05K3/38

CPC classification number: H05K3/4682 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H05K1/112 ,  H05K1/113 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/381 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/2072 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/1184 ,  H05K2203/308

Abstract: A wiring substrate includes an insulating layer that is an outermost layer of the wiring substrate and includes an external exposed surface, a pad forming part formed on a side of the external exposed surface, and a pad that projects from the external exposed surface. The pad forming part includes a recess part recessed from the external exposed surface, and a weir part that projects from the external exposed surface and encompasses the recess part from a plan view. The pad includes a pad body formed within the recess part and the weir part, and an eave part formed on the weir part. The pad body includes an end part that projects to the weir part. The eave part projects in a horizontal direction from the end part of the pad body. The end part of the pad body includes a flat surface.

Abstract translation: 布线基板包括绝缘层，其是布线基板的最外层，并且包括外部暴露表面，形成在外部暴露表面侧的焊盘形成部分以及从外部暴露表面突出的焊盘。 衬垫形成部分包括从外部暴露表面凹陷的凹陷部分和从外部暴露表面突出并从俯视图包围凹部的堰部分。 衬垫包括形成在凹部和堰部内的垫体，以及形成在堰部上的檐部。 垫体包括突出到堰部分的端部。 檐部从垫体的端部沿水平方向突出。 垫体的端部包括平坦表面。

公开(公告)号：US09395830B2

公开(公告)日：2016-07-19

申请号：US14125566

申请日：2012-06-15

Applicant: Kyung Hyun Jang ,  Hyung Bae Choi ,  Sung Jin Ryu ,  Ki Won Park

Inventor： Kyung Hyun Jang ,  Hyung Bae Choi ,  Sung Jin Ryu ,  Ki Won Park

IPC: H05K1/00 ,  G06F3/041 ,  G06F3/044 ,  G06F3/046 ,  H05K1/02 ,  H05K3/12

CPC classification number: G06F3/041 ,  G06F3/044 ,  G06F3/046 ,  G06F2203/04103 ,  H05K1/0296 ,  H05K3/1258 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2203/0108

Abstract: Disclosed is a wired electrode of touch screen panel for transmitting a touch signal sensed by a signal sensing pattern of touch screen panel to an external driving circuit, wherein the wired electrode formed on a substrate includes at least one curved portion, and a plurality of fine protrusions are formed on an inner surface of a groove of a resin layer on the substrate. The groove is filled with a conductive material to form the wired electrode.

Abstract translation: 公开了一种触摸屏面板的有线电极，用于将由触摸屏面板的信号感测图案感测的触摸信号发送到外部驱动电路，其中，形成在基板上的布线电极包括至少一个弯曲部分， 在基板上的树脂层的槽的内表面上形成突起。 凹槽填充有导电材料以形成布线电极。

公开(公告)号：US09295151B2

公开(公告)日：2016-03-22

申请号：US14000568

申请日：2012-02-01

Applicant: Masami Hasegawa ,  Satoshi Hirayama ,  Naoki Kito

Inventor： Masami Hasegawa ,  Satoshi Hirayama ,  Naoki Kito

IPC: H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  H01L23/13 ,  H01L23/10 ,  H01L23/498 ,  C04B41/00 ,  H05K1/14 ,  H01L23/15

CPC classification number: H05K1/0306 ,  C04B41/0036 ,  H01L23/10 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49805 ,  H01L2924/0002 ,  H05K1/14 ,  H05K3/0029 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/403 ,  H05K2201/017 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/0909 ,  H05K2201/09154 ,  H01L2924/00

Abstract: A wiring substrate includes a substrate main body which is formed of a ceramic laminate and has a rectangular shape in plan view, and which has a front surface and a back surface and has four side surfaces, each being located between the front surface and the back surface, and having a groove surface located on a side toward the front surface and a fracture surface located on a side toward the back surface; and a metalized layer which is formed on the front surface of the substrate main body so as to extend along the four side surfaces, and which has a rectangular frame shape in plan view, wherein a horizontal surface of the ceramic laminate of the substrate main body is exposed between the metalized layer and the groove surface of each side surface of the substrate main body.

Abstract translation: 布线基板包括由陶瓷层叠体形成的矩阵形状的基板主体，并且具有前表面和后表面，并且具有四个侧表面，每个侧表面位于前表面和背面之间 表面，并且具有位于朝向前表面的一侧的凹槽表面和位于朝向后表面的一侧的断裂表面; 以及金属化层，其形成在所述基板主体的前表面上，以便沿着所述四个侧表面延伸，并且在平面图中具有矩形框架形状，其中所述基板主体的陶瓷层叠体的水平表面 在金属化层与基板主体的各侧面的槽面之间露出。

公开(公告)号：US20150334844A1

公开(公告)日：2015-11-19

申请号：US14713063

申请日：2015-05-15

Applicant: IBIDEN CO., LTD

Inventor： Toyotaka SHIMABE ,  Ryuichiro Tominaga

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/03

CPC classification number: H05K1/185 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/032 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09045 ,  H05K2201/09854 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2203/1469 ,  Y02P70/611

Abstract: A printed wiring board includes a substrate having first and second cavities, first electronic components accommodated in the first cavity, second electronic components accommodated in the second cavity, and a build-up layer formed on the substrate and including an insulating interlayer such that the interlayer is covering the first and second cavities. The substrate has a first projection structure partitioning the first components in the first cavity and a second projection structure partitioning the second components in the second cavity, and the first and second cavities and the first and second projection structures are formed in the substrate such that T1

Abstract translation: 印刷电路板包括具有第一和第二空腔的衬底，容纳在第一腔中的第一电子部件，容纳在第二腔中的第二电子部件和形成在衬底上并包括绝缘夹层的堆积层， 覆盖第一和第二腔。 衬底具有分隔第一腔中的第一部件的第一突起结构和分隔第二腔中的第二部件的第二突出结构，并且第一和第二腔以及第一和第二突出结构形成在衬底中，使得T1 满足

公开(公告)号：US20150257260A1

公开(公告)日：2015-09-10

申请号：US14198658

申请日：2014-03-06

Applicant: Carolyn Rae Ellinger

Inventor： Carolyn Rae Ellinger

IPC: H05K1/02 ,  H05K1/09

CPC classification number: H05K1/0284 ,  C23C16/345 ,  C23C16/403 ,  C23C16/405 ,  C23C16/407 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2924/0002 ,  H05K1/09 ,  H05K2201/0137 ,  H05K2201/0326 ,  H05K2201/09045 ,  H01L2924/00

Abstract: A vertically separated electrode structure includes a polymeric material post on a substrate. An inorganic material cap covers the top of the post and extends beyond an edge of the post in at least a width dimension to define a first reentrant profile. A first electrode is located over the cap. A second electrode is located over the substrate and not over the post. The second electrode is adjacent to the edge of the post in the reentrant profile such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface. The first electrode and second electrode have the same material composition and layer thickness.

Abstract translation: 垂直分离的电极结构包括在基底上的聚合物材料柱。 无机材料盖覆盖柱的顶部并且在至少一个宽度尺寸上延伸超出柱的边缘以限定第一凹槽轮廓。 第一电极位于盖上。 第二电极位于衬底上并且不在柱上。 第二电极在折返轮廓中与柱的边缘相邻，使得当与衬底表面正交测量时，第一电极和第二电极之间的距离大于零。 第一电极和第二电极具有相同的材料组成和层厚度。

公开(公告)号：US20150147854A1

公开(公告)日：2015-05-28

申请号：US14259042

申请日：2014-04-22

Applicant: Electronics and Telecommunications Research Institute

Inventor： Soon-Won JUNG ,  Jae Bon KOO ,  Chan Woo PARK ,  Bock Soon NA ,  Sang Chul LIM ,  Sang Seok LEE ,  Kyoung Ik CHO ,  Hye Yong CHU

IPC: H01L21/311 ,  H01L29/66

CPC classification number: H01L21/311 ,  G09F9/301 ,  H01L29/66477 ,  H01L51/0023 ,  H01L51/0055 ,  H01L51/0525 ,  H01L51/102 ,  H05K1/0283 ,  H05K1/0333 ,  H05K1/16 ,  H05K3/0017 ,  H05K3/007 ,  H05K2201/0133 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/10166 ,  H05K2201/2009 ,  H05K2203/308

Abstract: Provided is a method of fabricating an electronic circuit. The method includes preparing a substrate, forming a polymer film on the substrate, patterning the polymer film to form a polymer pattern, and forming an electronic device on the polymer pattern.

Abstract translation: 提供一种制造电子电路的方法。 该方法包括制备基底，在基底上形成聚合物膜，图案化聚合物膜以形成聚合物图案，并在聚合物图案上形成电子器件。

公开(公告)号：US20150035433A1

公开(公告)日：2015-02-05

申请号：US14168036

申请日：2014-01-30

Applicant: UUSI, LLC d/b/a NARTRON

Inventor： David W. SHANK ,  John M. WASHELESKI ,  Edward J. COX, II

IPC: B60R16/02 ,  B60Q3/00 ,  H05B33/08 ,  H05K1/02

CPC classification number: H05B33/0803 ,  H05B33/086 ,  H05K1/02 ,  H05K1/117 ,  H05K1/142 ,  H05K1/16 ,  H05K2201/09027 ,  H05K2201/09045 ,  H05K2201/09081 ,  H05K2201/09154 ,  H05K2201/09163 ,  H05K2201/097 ,  H05K2201/09709 ,  H05K2201/0979 ,  H05K2201/0999 ,  H05K2201/10053 ,  H05K2201/10356

Abstract: An illustrative inventory of vehicle accessory control components includes a plurality of first circuit boards and a plurality of second circuit boards. The first circuit boards each have a substrate with a plurality of circuit elements supported on the substrate. The first circuit board substrates have an overall perimeter shape including an outer edge profile and a plurality of first deviations from the outer edge profile. The second circuit boards each have a substrate with a plurality of circuit elements supported on them. The second circuit board substrates have the overall perimeter shape including the same outer edge profile as the first circuit board substrates. The second circuit board substrates include a plurality of second deviations from the outer edge profile. At least one portion of the second deviations is different than the first deviations of the first circuit boards.

Abstract translation: 车辆附件控制部件的说明性库存包括多个第一电路板和多个第二电路板。 第一电路板各自具有支撑在基板上的多个电路元件的基板。 第一电路板基板具有包括外缘轮廓和从外边缘轮廓的多个第一偏离的总体周边形状。 第二电路板各自具有支撑在它们上的多个电路元件的基板。 第二电路板基板具有包括与第一电路板基板相同的外边缘轮廓的整体周边形状。 第二电路板基板包括与外边缘轮廓的多个第二偏差。 第二偏差的至少一部分不同于第一电路板的第一偏差。

公开(公告)号：US20150027753A1

公开(公告)日：2015-01-29

申请号：US14340564

申请日：2014-07-25

Applicant: Chun-Ming Huang ,  Yi-Chun Lin ,  Yi-Chen Tsai ,  Ming-Kung Wu

Inventor： Chun-Ming Huang ,  Yi-Chun Lin ,  Yi-Chen Tsai ,  Ming-Kung Wu

IPC: H05K1/02

CPC classification number: G06F3/041 ,  G06F2203/04103 ,  H05K1/0296 ,  H05K3/12 ,  H05K2201/0326 ,  H05K2201/0329 ,  H05K2201/09045 ,  H05K2201/09154 ,  H05K2201/09681 ,  H05K2201/09727

Abstract: A panel structure includes a substrate, a decoration layer and a conductive component. The decoration layer is located in a first region and the rest region is a second region. The decoration layer includes a middle portion and a first edge protruding portion located between the middle portion and the second region and thinner than the middle portion. Each the conductive component extends in a first direction towards the first region from the second region and crosses the first edge protruding portion followed by extending in a second direction on the middle portion of the decoration layer, the first direction intersects the second direction, each the conductive component on the first edge protruding portion has a first width, each the conductive component on the middle portion extends in the second direction and has a second width less than the first width.

Abstract translation: 面板结构包括基板，装饰层和导电部件。 装饰层位于第一区域中，其余区域是第二区域。 装饰层包括位于中间部分和第二区域之间的中间部分和第一边缘突出部分，并且比中间部分薄。 每个导电部件沿着第一方向从第二区域朝向第一区域延伸，并且穿过第一边缘突出部分，然后在装饰层的中间部分上沿第二方向延伸，第一方向与第二方向相交， 第一边缘突出部分上的导电部件具有第一宽度，中间部分上的导电部件在第二方向上延伸，并且具有小于第一宽度的第二宽度。

公开(公告)号：US20140367837A1

公开(公告)日：2014-12-18

申请号：US14303371

申请日：2014-06-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Che LEE ,  Yuan-Chang SU ,  Wen-Chi CHENG ,  Guo-Cheng LIAO ,  Yi-Chuan DING

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/11622 ,  H01L2224/1163 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2203/0723 ,  H05K2203/1461 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

Abstract translation: 本公开涉及一种半导体衬底及其制造方法。 半导体衬底包括绝缘层，第一电路层，第二电路层，多个导电通孔和多个凸块。 第一电路层嵌入绝缘层的第一表面，并从绝缘层的第一表面露出。 第二电路层位于绝缘层的第二表面上，并通过导电通孔与第一电路层电连接。 凸块直接位于第一电路层的一部分上，其中凸块的晶格与第一电路层的晶格相同。

公开(公告)号：US20140199522A1

公开(公告)日：2014-07-17

申请号：US13744187

申请日：2013-01-17

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Richard Coull ,  Kevin Dooley ,  David Fitzpatrick

IPC: B32B3/30 ,  B32B5/16

CPC classification number: H05K3/1258 ,  G03F7/0002 ,  H05K1/097 ,  H05K2201/09036 ,  H05K2201/09045 ,  Y10T428/24479 ,  Y10T428/24579

Abstract: Devices with nanosized particles deposited on shaped surface geometries include a substrate with an active material of nanosized particles deposited on a surface of the substrate. The active material has an edge formed at a position determined with a shaped geometry of the surface.

Abstract translation: 沉积在成形表面几何上的纳米尺寸颗粒的装置包括具有沉积在基底表面上的纳米尺寸颗粒的活性材料的基底。 活性材料具有形成在由表面的成形几何形状确定的位置处的边缘。