公开(公告)号：US20090242259A1

公开(公告)日：2009-10-01

申请号：US12409609

申请日：2009-03-24

Applicant: Voonyee HO ,  Katsutoshi KAMEI

Inventor： Voonyee HO ,  Katsutoshi KAMEI

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K1/0221 ,  H05K1/0218 ,  H05K1/056 ,  H05K3/4647 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2203/0733 ,  Y10T29/49155

Abstract: Ground traces are formed to sandwich a write wiring trace. Ground walls are formed on the ground traces. A ground cover is formed so as to couple upper ends of the ground walls. Thus, the ground traces, the ground walls and the ground cover are positioned in a region above and on both sides of the write wiring trace to surround the write wiring trace.

Abstract translation: 形成接地迹线以夹住写入线迹。 地面上的痕迹形成在地面上。 形成地盖以便联接地面壁的上端。 因此，接地迹线，接地墙和接地盖位于写入布线迹线的上方和两侧的区域中，以包围写入布线迹线。

公开(公告)号：US20090242244A1

公开(公告)日：2009-10-01

申请号：US12126748

申请日：2008-05-23

Applicant: SHOU-KUO HSU ,  CHUN-JEN CHEN

Inventor： SHOU-KUO HSU ,  CHUN-JEN CHEN

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09336

Abstract: An exemplary PCB includes a first reference layer, a first signal layer, and a second signal layer in that order. A first differential pair is arranged in the first signal layer in an edge-coupled structure referencing the first reference layer. A second differential pair is arranged in the second signal layer in edge-coupled structure. A first ground part and a second ground part are symmetrically arranged at opposite sides of the second differential pair in the second signal layer. The first differential pair is arranged above the first ground part and a projection of the first differential pair onto the second signal layer having an area coincident with the first ground part. The second differential pair references the first and second ground parts.

Abstract translation: 示例性的PCB包括第一参考层，第一信号层和第二信号层。 第一差分对以参考第一参考层的边缘耦合结构布置在第一信号层中。 第二差分对以边缘耦合结构布置在第二信号层中。 第一接地部分和第二接地部分对称地布置在第二信号层中的第二差分对的相对侧。 第一差分对布置在第一接地部分的上方，并且第一差分对的突起与具有与第一接地部分重合的区域的第二信号层上。 第二差分对参考第一和第二接地部分。

公开(公告)号：US07595546B2

公开(公告)日：2009-09-29

申请号：US11548431

申请日：2006-10-11

Applicant: Shoji Matsumoto

Inventor： Shoji Matsumoto

IPC: H01L23/64 ,  H05K7/00 ,  H04B3/28

CPC classification number: H05K1/0216 ,  H01L2924/0002 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/10689 ,  H01L2924/00

Abstract: Impedance mismatching points such as a VIA and a connector on a differential line between a differential driver element and a differential receiver element are arranged in predetermined positions. That is, the impedance mismatching points are arranged in such positions that a transmission time of a digital signal transmitted through a main differential line becomes (integral multiple of UI)±0.5×Trf, whereby noises are generated within the rise and fall times of a signal to be able to maintain an excellent waveform of the signal.

Abstract translation: 诸如差分驱动器元件和差分接收器元件之间的差分线路上的VIA和连接器的阻抗不匹配点被布置在预定位置。 也就是说，阻抗失配点被布置在通过主差分线发送的数字信号的发送时间变为（UI的整数倍）±0.5×Trf的位置，从而在信号的上升和下降时间内产生噪声 能够保持良好的信号波形。

公开(公告)号：US20090229859A1

公开(公告)日：2009-09-17

申请号：US12075375

申请日：2008-03-11

Applicant: Dorin Oprea ,  Steven Driediger

Inventor： Dorin Oprea ,  Steven Driediger

IPC: H05K1/00

CPC classification number: H05K1/0218 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/10121

Abstract: The present invention is a specially designed PCB that allows XFP compliant transceiver modules and EMI gaskets to be used in a manner specified in the XFP standard and results in an integrated solution that is compliant with the XFP standard. Various geometric features are incorporated into the PCB to achieve improvements that in combination result in an integrated solution meeting the XFP standard. Some of these improved features include: specific thickness of prepreg and other layering of the PCB, specific spacing, dimensions and weights for certain components of the PCB, an opening on the first layer XFP cage ground shield connecting to the EMI gasket, guard ground traces in the second layer surrounding the differential pair signal traces, openings in the copper of the third layer beneath the XFP cage ground shield and XFP connector pads, and ground vias at the XFP connector and PHY connector pads.

Abstract translation: 本发明是专门设计的PCB，其允许以XFP标准中规定的方式使用符合XFP标准的收发器模块和EMI垫片，并产生符合XFP标准的集成解决方案。 各种几何特征被并入到PCB中以实现改进，其结合形成满足XFP标准的集成解决方案。 其中一些改进的特征包括：预浸料坯的特定厚度和PCB的其他分层，PCB的某些部件的特定间距，尺寸和重量，第一层上的开口XFP笼式接地屏蔽层连接到EMI垫片，保护接地迹线 在围绕差分对信号迹线的第二层中，XFP笼式接地屏蔽和XFP连接器焊盘下方第三层铜的开口，以及XFP连接器和PHY连接器焊盘处的接地通孔。

公开(公告)号：US20090204934A1

公开(公告)日：2009-08-13

申请号：US12030667

申请日：2008-02-13

Applicant: Yu-Sen Lin

Inventor： Yu-Sen Lin

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  H05K1/0245 ,  H05K1/0248 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09263

Abstract: A method for compensating length of differential pair and a method for calculating compensation length of the zigzagging type delay line thereof are provided. The method for calculating compensation length of the zigzagging type delay line includes following steps. The quantity A of hypotenuse and the quantity B of bends of the zigzagging type delay line are counted. The width W of the zigzagging type delay line is measured. The height S1 of the parallel line segment of the zigzagging type delay line is measured. An equation L diff = A ( 2 - 1 )  ( S 1 - ( 5  W / 6 ) ) + B  { [ W 5  ( 1 + 2 ) ] 2 + [ W 5 ] 2 - [ W 5  ( 1 + 2 ) ] } is calculated for calculating the compensation length Ldiff of the zigzagging type delay line.

公开(公告)号：US07573721B2

公开(公告)日：2009-08-11

申请号：US11749752

申请日：2007-05-17

Applicant: Ting-Hao Lin ,  Chien-Wei Chang

Inventor： Ting-Hao Lin ,  Chien-Wei Chang

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/108 ,  H05K3/205 ,  H05K2201/09236 ,  H05K2201/09881 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: Embedded passive device structure and its manufacturing method for mainly embedding the passive device structure in the printed circuit board are presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.

Abstract translation: 介绍了嵌入式无源器件结构及其主要将无源器件结构嵌入印刷电路板的制造方法。 在该结构中，无源器件的源电极和接地电极都属于同一水平，并且包括垂直形成在电路板的电介质层的内部的多个源极分支和几个接地分支， 以避免在层压期间源电极和接地电极之间的导电。 当它是电容器结构的形式时，通过使用超细布线技术，这些源极分支和接地分支之间彼此间有很小的间隙。 因此，源分支和接地分支的侧面积和数量都增加。

公开(公告)号：US20090195935A1

公开(公告)日：2009-08-06

申请号：US12179786

申请日：2008-07-25

Applicant: Ho-joong CHOI

Inventor： Ho-joong CHOI

IPC: G11B5/48

CPC classification number: G11B5/4853 ,  H05K1/0216 ,  H05K1/056 ,  H05K3/28 ,  H05K2201/09236 ,  H05K2201/0989

Abstract: A suspension interconnect of a head gimbal assembly (HGA) includes a ground layer; a base layer formed of a dielectric material and disposed on the ground layer; a pair of read traces and a pair of write traces which are formed of a conductive material, disposed on the base layer to extend so as not to short each other; and a cover layer which are formed of a dielectric material, disposed on the base layer and the traces and are to seal the traces, wherein the cover layer includes a read cover layer which is to seal the read traces, and a write cover layer which is separated from the read cover layer and to seal the write traces.

Abstract translation: 头万向节组件（HGA）的悬挂互连包括接地层; 由介电材料形成并设置在接地层上的基层; 一对读取迹线和由导电材料形成的一对写入迹线，其设置在基底层上以便彼此不彼此缩短; 以及覆盖层，其由介电材料形成，设置在基底层和迹线上并且用于密封迹线，其中覆盖层包括用于密封读取的迹线的读取覆盖层和写入覆盖层， 与读取覆盖层分离并密封写入轨迹。

公开(公告)号：US20090193383A1

公开(公告)日：2009-07-30

申请号：US12021363

申请日：2008-01-29

Applicant: Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhou

Inventor： Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhou

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0237 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: An auto routing method and system provides optimized circuit routing while maintaining proper reference return paths for critical signals. Critical signal paths are auto-routed simultaneously with corresponding reference return paths, and the reference return paths can be merged into reference planes if they are adjacent to regions connected to the same reference net. The reference return paths may be in a plane adjacent to the signal path plane in the same channel, or the reference returns may be routed in adjacent channels in the same plane as the signal path. A check may be performed on endpoints of each critical signal path to determine whether a reference return via is present within a proximity tolerance of the signal path endpoints, and a reference return via placed if not.

Abstract translation: 自动路由方法和系统提供优化的电路路由，同时为关键信号保留适当的参考返回路径。 临界信号路径与对应的参考返回路径同时自动路由，并且如果参考返回路径与连接到相同参考网络的区域相邻，则它们可以合并到参考平面中。 参考返回路径可以在与相同信道中的信号路径平面相邻的平面中，或者参考返回可以在与信号路径相同的平面中的相邻信道中路由。 可以在每个关键信号路径的端点上执行检查，以确定参考返回通道是否存在于信号路径端点的接近容限内，如果不是则通过放置参考返回。

公开(公告)号：US20090187874A1

公开(公告)日：2009-07-23

申请号：US12015627

申请日：2008-01-17

Applicant: Mao-Lin Wu ,  Shih-Hung Lin ,  Hua Wu ,  Che Yuan Jao ,  Ching-Chih Li ,  Sheng-Ming Chang

Inventor： Mao-Lin Wu ,  Shih-Hung Lin ,  Hua Wu ,  Che Yuan Jao ,  Ching-Chih Li ,  Sheng-Ming Chang

IPC: G06F17/50

CPC classification number: H05K1/0216 ,  H01R12/79 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/10166 ,  H05K2201/10689

Abstract: A circuit and a circuit design method are provided. The circuit operates between a first power source voltage and a ground voltage. The circuit comprises at least one low speed circuit path and at least one high speed circuit path. The low speed circuit path adjusts voltage level at the first power source voltage or the ground voltage. The low speed circuit path provides a first return path and isolates unwanted noise signals for a signal on the high speed circuit path.

Abstract translation: 提供电路和电路设计方法。 该电路在第一电源电压和接地电压之间工作。 该电路包括至少一个低速电路路径和至少一个高速电路路径。 低速电路路径调整第一电源电压或接地电压时的电压电平。 低速电路路径提供第一返回路径并隔离高速电路路径上的信号的不需要的噪声信号。

公开(公告)号：US07564695B2

公开(公告)日：2009-07-21

申请号：US12144595

申请日：2008-06-23

Applicant: Shoji Matsumoto

Inventor： Shoji Matsumoto

IPC: H05K9/00

CPC classification number: H05K1/0224 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: While gradually increasing the widths of signal lines (104a, 104b, 105a, 105b) of first and second groups of differential signal lines (104, 105) to suppress attenuation in the lines, the opening widths of slits (104s, 105s) formed in a GND layer (102) below the differential signal lines are similarly changed. Thereby, impedance matching is realized. Further, by alternately disposing a large-width side and a small-width side of the two groups of differential signal lines (104, 105), the total wiring area widths are reduced.

Abstract translation: 在逐渐增加第一组和第二组差分信号线（104,105）的信号线（104a，104b，105a，105b）的宽度以抑制线中的衰减的同时，形成的狭缝（104s，105s）的开口宽度 类似地，差分信号线下面的GND层（102）也被改变。 从而实现阻抗匹配。 此外，通过交替地设置两组差分信号线（104,105）的大宽度侧和小宽度侧，总布线面积宽度减小。