公开(公告)号：US06417460B1

公开(公告)日：2002-07-09

申请号：US09800412

申请日：2001-03-06

Applicant: Yu-Chiang Cheng

Inventor： Yu-Chiang Cheng

IPC: H05K103

CPC classification number: H05K1/024 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/4688 ,  H05K2201/0145 ,  H05K2201/0191 ,  H05K2201/09327

Abstract: A multi-layer circuit board includes first, second, third, fourth, fifth, sixth and seventh insulating substrates; first, second, third, fourth and fifth signal wiring layers; first and second ground wiring layers; and a power wiring layer. Each of the first and seventh insulating substrates has a thickness ranging from 2.5 to 6.5 mil. Each of the second, fourth and sixth insulating substrates has a thickness ranging from 3 to 9 mil. Each of the third and fifth insulating substrates has a thickness ranging from 3 to 23 mil. The first signal wiring layer has a first resistance with respect to the first ground wiring layer. The second signal wiring layer has a second resistance with respect to the first ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the first ground wiring layer and the power wiring layer. The fourth signal wiring layer has a fourth resistance with respect to the second ground wiring layer and the power wiring layer. The fifth signal wiring layer has a fifth resistance with respect to the second ground wiring layer. The first, second, third, fourth and fifth resistances are within the range of 49.5 to 60.5 ohms.

Abstract translation: 多层电路板包括第一，第二，第三，第四，第五，第六和第七绝缘基板; 第一，第二，第三，第四和第五信号布线层; 第一和第二接地布线层; 和电力布线层。 第一和第七绝缘基板中的每一个具有2.5至6.5密耳的厚度。 第二，第四和第六绝缘基板中的每一个具有3至9密耳的厚度。 第三和第五绝缘基板中的每一个具有3至23密耳的厚度。 第一信号布线层相对于第一接地布线层具有第一电阻。 第二信号布线层相对于第一接地布线层和电源布线层具有第二电阻。 第三信号布线层相对于第一接地布线层和电源布线层具有第三电阻。 第四信号布线层相对于第二接地布线层和电源布线层具有第四电阻。 第五信号布线层相对于第二接地布线层具有第五电阻。 第一，第二，第三，第四和第五电阻在49.5至60.5欧姆的范围内。

公开(公告)号：US06359237B1

公开(公告)日：2002-03-19

申请号：US09637684

申请日：2000-08-14

Applicant: Hirokazu Tohya ,  Shiro Yoshida

Inventor： Hirokazu Tohya ,  Shiro Yoshida

IPC: H01R909

CPC classification number: H05K1/0248 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09263 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/10689

Abstract: In order to reduce electromagnetic inductive interference due to power source current, in a multi-layer printed board on which a multiplicity of high-speed and high-frequency circuit elements are mounted, a multi-layer printed board has a construction such that on both upper and lower sides of a power source layer 1 provided with power source wiring 6, are laminated ground layers 2 via respective first insulating material layers 4, and on one or both of the upper and lower sides of these is laminated a signal layer 3 provided with signal wiring, via a second insulating material layer 5.

Abstract translation: 为了减少由于电源电流引起的电磁感应干扰，在多层印刷电路板上安装有多个高速和高频电路元件的情况下，多层印刷电路板具有这样的结构： 设置有电源布线6的电源层1的上侧和下侧经由各自的第一绝缘材料层4层叠接地层2，并且在它们的上侧和下侧的一侧或两侧层叠有提供的信号层3 具有信号线，经由第二绝缘材料层5。

公开(公告)号：US06229095B1

公开(公告)日：2001-05-08

申请号：US09408268

申请日：1999-09-29

Applicant: Naoki Kobayashi

Inventor： Naoki Kobayashi

IPC: H05K103

CPC classification number: H05K1/116 ,  H05K1/0216 ,  H05K3/429 ,  H05K2201/09327 ,  H05K2201/09718 ,  H05K2201/10689

Abstract: A multilayer wiring board of this invention includes first and second power source patterns of a first potential and a third power source pattern of a second potential. A wiring pattern formed in a signal wiring layer is positioned between the first power source pattern of the first potential and the third power source pattern of the second potential. A hole is connected to the wiring pattern and passes through the first and second power source patterns of the first potential and the third power source pattern of the second potential. A first gap is formed between the first power source pattern of the first potential and the hole. A second gap is formed between the second power source pattern of the first potential and the through hole and is larger than the first gap. Another multilayer wiring board of the present invention includes a top surface, a signal wiring provided on the top surface, a first power source pattern formed in a first power source layer in a position which is the closest to the signal wiring, a second power source pattern formed in a second power source layer and a hole which is connected to the signal wiring and passes through the first and second power source patterns. A first gap is formed between the first power source pattern and the through hole. A second gap is formed between the second power source pattern and the through hole and is larger than the first gap.

Abstract translation: 本发明的多层布线基板包括具有第一电位的第一和第二电源图案和第二电位的第三电源图案。 形成在信号布线层中的布线图案位于第一电位的第一电源图案和第二电位的第三电源图案之间。 一个孔连接到布线图案，并通过第一电位和第二电位的第三电源图案的第一和第二电源图案。 在第一电位的第一电源图案和孔之间形成第一间隙。 在第一电位的第二电源图形与通孔之间形成第二间隙，并且大于第一间隙。 另外，本发明的多层布线基板包括上表面，设置在上表面的信号布线，形成在与信号布线最接近的位置的第一电源层中的第一电源图案，第二电源 形成在第二电源层中的图案和连接到信号布线并穿过第一和第二电源图案的孔。 在第一电源图案和通孔之间形成第一间隙。 在第二电源图案和通孔之间形成第二间隙，并且大于第一间隙。

公开(公告)号：US5451721A

公开(公告)日：1995-09-19

申请号：US764733

申请日：1991-09-24

Applicant: Yutaka Tsukada ,  Shuhei Tsuchida

Inventor： Yutaka Tsukada ,  Shuhei Tsuchida

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/18 ,  H05K3/42 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K3/4602 ,  H05K1/0265 ,  H05K2201/0352 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2203/1438 ,  H05K2203/1581 ,  H05K3/0023 ,  H05K3/181 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4661 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayer printed circuit board and a corresponding fabrication method are disclosed, which circuit board achieves a relatively high degree of wiring density and a relatively high degree of wiring design freedom. These advantages are obtained in the inventive printed circuit board by electrically connecting power conductors or ground conductors using through holes. On the other hand, signal conductors in any two adjacent signal wiring layers are electrically connected using via holes extending only through an intervening electrically insulating layer. Preferably, the electrically insulating layer is a layer of photosensitive resin and the via holes are formed using conventional photolithographic techniques.

Abstract translation: 公开了一种多层印刷电路板和相应的制造方法，该电路板实现相对高的布线密度和相对高的布线设计自由度。 通过使用通孔电连接电源导体或接地导体，在本发明的印刷电路板中获得这些优点。 另一方面，任何两个相邻信号布线层中的信号导体使用仅通过中间电绝缘层延伸的通孔电连接。 优选地，电绝缘层是感光树脂层，并且通孔使用常规的光刻技术形成。

公开(公告)号：US5371653A

公开(公告)日：1994-12-06

申请号：US29919

申请日：1993-03-11

Applicant: Masatsugu Kametani ,  Kazuhiro Umekita

Inventor： Masatsugu Kametani ,  Kazuhiro Umekita

IPC: H05K1/11 ,  H01L23/467 ,  H01L23/538 ,  H05K1/02 ,  H05K3/34 ,  H05K3/42 ,  H05K3/46 ,  H05K7/20

CPC classification number: H05K1/0207 ,  H01L23/467 ,  H01L23/5383 ,  H01L23/5384 ,  H05K3/429 ,  H05K3/4641 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0201 ,  H05K1/0206 ,  H05K2201/0209 ,  H05K2201/0352 ,  H05K2201/062 ,  H05K2201/09327 ,  H05K2201/09581 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09881 ,  H05K2201/10689 ,  H05K3/3447

Abstract: A circuit board includes a circuit-conductor layer, a ground layer and a power source layer superposed in a multilayer form through dielectric layers therebetween, A heat conduction through inside of the circuit board is enhanced so that circuit chips mounted on the circuit board can be cooled down to a level capable of operating normally, The circuit board can be formed to be compact, In order to enhance the heat transfer in the circuit board, at least one of the ground layer and power source layer is formed in a multilayer manner, It is preferable to form these layers at a thickness larger than that of the circuit-conductor layer, Further, preferably, the pin of the chip mounted on the board and at least one of the ground layer and power supply layer are connected to each other in such a manner as to enhance the heat conduction.

Abstract translation: 电路板包括电路导体层，接地层和电源层，通过其间的介电层叠加成多层形式。通过电路板内部的热传导增强，使得安装在电路板上的电路芯片可以 冷却到能够正常工作的水平。电路板可以形成为紧凑的。为了增强电路板中的热传递，接地层和电源层中的至少一个以多层形式形成， 优选以比电路导体层的厚度大的方式形成这些层。此外，优选地，安装在基板上的芯片的引脚和接地层和电源层中的至少一个彼此连接 以增强热传导的方式。

公开(公告)号：US5061824A

公开(公告)日：1991-10-29

申请号：US397706

申请日：1989-08-23

Applicant: Arthur R. Alexander ,  Paul M. Rostek

Inventor： Arthur R. Alexander ,  Paul M. Rostek

IPC: G06F3/00 ,  G06F13/40 ,  H01P3/08 ,  H05K1/00 ,  H05K1/02 ,  H05K3/46 ,  H05K9/00

CPC classification number: G06F13/40 ,  H05K1/0216 ,  H05K1/0237 ,  H05K9/0039 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09327 ,  H05K2201/09727 ,  H05K2201/09972

Abstract: A printed circuit board backpanel uses stripline construction to allow emitter coupled logic. (ECL) signals and transistor-transistor logic (TTL) signals on the same signal layer, while providing electromagnetic interference (EMI) emission control.

公开(公告)号：US4710854A

公开(公告)日：1987-12-01

申请号：US24894

申请日：1987-03-10

Applicant: Minoru Yamada ,  Motoyo Wajima ,  Akira Masaki ,  Akio Takahashi ,  Keiichirou Nakanishi ,  Katuo Sugawara

Inventor： Minoru Yamada ,  Motoyo Wajima ,  Akira Masaki ,  Akio Takahashi ,  Keiichirou Nakanishi ,  Katuo Sugawara

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H05K1/14

CPC classification number: H05K3/4626 ,  H05K1/024 ,  H05K1/0237 ,  H05K1/0346 ,  H05K1/115 ,  H05K2201/015 ,  H05K2201/0158 ,  H05K2201/0191 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K3/4623

Abstract: A multilayer wiring board structure includes a plurality of conductor layers and insulation layers interleaved between each ones of the conductor layers. The conductor layers includes power (or ground) line layers and signal line layers, and one type of insulation layer having lower relative permittivity and another type of insulation layer having higher relative permittivity is used between power (ground) line layers interposed by signal line layer(s).

Abstract translation: 多层布线板结构包括在每个导体层之间交错的多个导体层和绝缘层。 导体层包括功率（或接地）线层和信号线层，并且在由信号线层插入的功率（接地）线层之间使用具有较低相对介电常数的一种类型的绝缘层和具有较高相对介电常数的另一种类型的绝缘层 （s）。

公开(公告)号：US4553111A

公开(公告)日：1985-11-12

申请号：US527841

申请日：1983-08-30

Applicant: Michael Barrow

Inventor： Michael Barrow

IPC: H01P3/08 ,  H05K1/00 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H01P5/00

CPC classification number: H01P3/081 ,  H01P3/088 ,  H05K1/025 ,  H05K3/46 ,  H05K1/0289 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09609 ,  H05K3/429

Abstract: A multilayer printed circuit board for TTL logic components provides an approximate 100 ohm characteristic impedance between external microstrip signal lines and internal ground and voltage planes. The addition of two internal microstrip signal plane lines permits a much greater interconnectability capability and also saves a large percentage of spatial area for component mounting while still maintaining the 100 ohm impedance characteristic.

Abstract translation: 用于TTL逻辑元件的多层印刷电路板在外部微带线信号线和内部接地和电压平面之间提供约100欧姆的特性阻抗。 添加两个内部微带信号平面线允许更大的互连能力，并且还可以节省用于部件安装的大部分空间面积，同时仍然保持100欧姆的阻抗特性。

公开(公告)号：US4328531A

公开(公告)日：1982-05-04

申请号：US134623

申请日：1980-03-27

Applicant: Toshio Nagashima ,  Takeshi Saitoh ,  Hiroshi Hatashita ,  Mitsuhisa Shinagawa

Inventor： Toshio Nagashima ,  Takeshi Saitoh ,  Hiroshi Hatashita ,  Mitsuhisa Shinagawa

IPC: H03J5/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K3/4667 ,  H05K1/0218 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/09327

Abstract: A thick film multilayer substrate using a green ceramic sheet is constructed such that at least three conductor layers and at least two dielectric layers are alternately arranged in turn on the green ceramic sheet substrate, a power supply line being formed in the second conductor layer and thus interposed between the first and third conductor layers in which grounded conductors are formed.

Abstract translation: 使用生坯陶瓷片的厚膜多层基板被构造成使得至少三个导体层和至少两个电介质层依次在绿色陶瓷片基板上交替布置，电源线形成在第二导体层中，因此 介于形成有接地导体的第一和第三导体层之间。