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公开(公告)号：US09620447B2
公开(公告)日：2017-04-11
申请号：US15059948
申请日：2016-03-03
Applicant: Renesas Electronics Corporation
Inventor： Shuuichi Kariyazaki , Ryuichi Oikawa
IPC: H01L23/498 , H05K1/02 , H01L23/522 , H01L23/00
CPC classification number: H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5225 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/0401 , H01L2224/05082 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05644 , H01L2224/05655 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/14135 , H01L2224/16057 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2224/83104 , H01L2924/1517 , H01L2924/15311 , H05K1/0225 , H05K1/0253 , H05K2201/09336 , H05K2201/09681 , H01L2924/014 , H01L2924/00014 , H01L2924/00
Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.
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公开(公告)号：US20160366759A1
公开(公告)日：2016-12-15
申请号：US14461900
申请日：2014-08-18
Applicant: Cray Inc.
Inventor： Hyunjun Kim , Jeffrey Scott Conger , Gregory Erwin Scott
CPC classification number: H05K1/0225 , H05K1/0219 , H05K1/0222 , H05K1/0245 , H05K1/0298 , H05K1/114 , H05K1/115 , H05K3/4007 , H05K3/42 , H05K2201/093 , H05K2201/09336 , H05K2201/09609 , H05K2201/09618 , Y10T29/49155 , Y10T29/49165
Abstract: A multi-layer printed circuit board has a number of landing pads that are configured to engage a connector secured thereto. Between the landing pads associated with different signals is at least one micro via that is electrically connected to a ground plane on an outer surface of the multi-layer printed circuit board, and a ground plane on an inner layer of the multi-layer printed circuit board.
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公开(公告)号：US20160164158A1
公开(公告)日：2016-06-09
申请号：US14559503
申请日：2014-12-03
Applicant: QUALCOMM Incorporated
Inventor： Darryl JESSIE , Lan NAN
IPC: H01P3/02 , H01P11/00 , H01L23/528 , H01L23/66 , H01L21/768 , H01P3/08 , H01L23/00
CPC classification number: H01P3/006 , H01L21/768 , H01L23/5225 , H01L23/525 , H01L23/528 , H01L23/66 , H01L24/11 , H01L24/14 , H01L2223/6605 , H01L2223/6627 , H01P3/003 , H05K1/0219 , H05K2201/0305 , H05K2201/09236 , H05K2201/09336 , H05K2201/09618
Abstract: In an integrated circuit package that houses radio-frequency (RF) circuits or components using wafer-level packaging (WLP), an RF-signal transmission structure includes a signal-carrying conductive line positioned between grounded conductive lines to avoid undesirable coupling between the signal-carrying conductive line and other RF circuits or components in the same package.
Abstract translation: 在使用晶片级封装（WLP）容纳射频（RF）电路或部件的集成电路封装中，RF信号传输结构包括位于接地导线之间的信号承载导线，以避免信号之间的不期望的耦合 - 同一封装中的导线和其他RF电路或组件。
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公开(公告)号：US09345128B2
公开(公告)日：2016-05-17
申请号：US13508209
申请日：2010-11-04
Applicant: Kent E. Regnier
Inventor： Kent E. Regnier
IPC: H01R13/646 , H05K1/00 , H05K1/02 , H01R13/6469 , H01R13/66 , H01R107/00 , H05K3/34 , H05K3/42
CPC classification number: H05K1/0227 , H01R13/6466 , H01R13/6469 , H01R13/6625 , H01R13/6633 , H01R2107/00 , H03H7/09 , H05K1/0233 , H05K1/0245 , H05K1/0248 , H05K1/115 , H05K3/3447 , H05K3/429 , H05K2201/09263 , H05K2201/09309 , H05K2201/09336 , H05K2201/09663 , H05K2201/1006 , H05K2201/10189 , H05K2201/10371 , H05K2203/0307
Abstract: A multi-layer circuit member includes a conductive reference plane with first and second electrically connected regions. A pair of signal conductors are in proximity to the first region and a circuit component is in proximity to the second region. An area of increased impedance exists between the first and second electrically connected regions.
Abstract translation: 多层电路构件包括具有第一和第二电连接区域的导电参考平面。 一对信号导体靠近第一区域，电路部件接近第二区域。 在第一和第二电连接区域之间存在增加阻抗的区域。
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公开(公告)号：US20160088723A1
公开(公告)日：2016-03-24
申请号：US14838355
申请日：2015-08-27
Applicant: KUANG YING COMPUTER EQUIPMENT CO., LTD.
Inventor： HSUAN-HO CHUNG , CHIEN-LING TSENG
CPC classification number: H05K1/144 , H05K1/0219 , H05K1/0225 , H05K1/0245 , H05K1/117 , H05K2201/042 , H05K2201/09336 , H05K2201/09718 , H05K2201/10189 , H05K2201/10446
Abstract: A stack structure of a high frequency printed circuit, mainly includes a transmission conductor pin group in a form of single row, where each signal pair and each transmission pair of the transmission conductor pin group respectively have a through hole portion thereon, and the inner layer of the circuit board has a trace portion in electric connection with the through hole portion, allowing each four terminals to be formed into one group. Utilizing the clever arrangement of the through hole portions and trace portions separates each terminal properly, thereby increasing the property of transmitted signals, and, at the same time, reducing noise interferences such as EMI and RFI.
Abstract translation: 高频印刷电路的堆叠结构主要包括单列形式的发送导体引脚组，其中每个信号对和发送导体引脚组的每个传输对在其上分别具有通孔部分，并且内层 电路板具有与通孔部分电连接的迹线部分，允许将四个端子形成为一组。 利用通孔部分和迹线部分的巧妙布置正确地分离每个端子，从而增加了传输信号的性质，同时降低了EMI和RFI等噪声干扰。
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Patent Agency Ranking
公开(公告)号：US09282632B2
公开(公告)日：2016-03-08
申请号：US13861907
申请日：2013-04-12
Applicant: TAIYO YUDEN CO., LTD.
Inventor： Tetsuo Saji , Hiroshi Nakamura
CPC classification number: H05K1/0253 , H01P3/088 , H05K1/0227 , H05K1/185 , H05K3/4602 , H05K2201/09245 , H05K2201/09336 , H05K2201/09727
Abstract: A multilayer circuit substrate includes: a first conductor layer in which first transmission lines and a second transmission line are formed; a second conductive layer facing the first conductive layer through an insulating layer; and a third conductive layer that faces the second conductive layer through an insulating layer and that has a bypass line formed therein. The bypass line is electrically connected to the second transmission line of the first conductive layer through via conductors and such that the second transmission line and the first transmission lines intersect with each other. In the second conductive layer, a ground conductor is formed at least in a position that faces the bypass line, and the first transmission lines are made narrower at the intersection with the second transmission line than other portions.
Abstract translation: 多层电路基板包括：第一导体层，其中形成有第一传输线和第二传输线; 通过绝缘层面对所述第一导电层的第二导电层; 以及通过绝缘层面向所述第二导电层并且在其中形成有旁路线的第三导电层。 旁通线路通过通孔导体与第一导电层的第二传输线电连接，使得第二传输线与第一传输线相互交叉。 在第二导电层中，至少形成面向旁路线的位置的接地导体，并且使第一传输线在与第二传输线的交点处比其它部分更窄。
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公开(公告)号：US20150351257A1
公开(公告)日：2015-12-03
申请号：US14722246
申请日：2015-05-27
Applicant: KYOCERA Circuit Solutions, Inc.
Inventor： Kohichi OHSUMI , Kazuki OKA
CPC classification number: H05K3/4644 , H05K3/108 , H05K2201/0347 , H05K2201/09336 , H05K2201/09509 , H05K2201/09545 , H05K2201/09563 , H05K2201/09681 , H05K2203/025 , H05K2203/0723 , H05K2203/1476
Abstract: A method for producing a wiring board includes the steps of forming an upper insulating layer on a lower insulating layer having a lower wiring conductor on its upper surface; forming a via-hole in the upper insulating layer; depositing a first base metal layer in the via-hole and on an upper surface of the upper insulating layer; forming a first plating resist layer on the first base metal layer; depositing a first electrolytically plated layer to completely fill at least the via-hole; forming a via conductor, and depositing a second base metal layer; forming a second plating resist layer on the second base metal layer; depositing a second electrolytically plated layer; and forming a wiring pattern.
Abstract translation: 制造布线板的方法包括以下步骤：在其上表面上形成具有下布线导体的下绝缘层上的上绝缘层; 在上绝缘层中形成通孔; 在所述通孔中和所述上绝缘层的上表面上沉积第一基底金属层; 在所述第一基底金属层上形成第一电镀抗蚀剂层; 沉积第一电解镀层以至少完全填充通孔; 形成通孔导体，并沉积第二基底金属层; 在所述第二基底金属层上形成第二电镀抗蚀剂层; 沉积第二电解镀层; 并形成布线图案。
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公开(公告)号：US09198279B2
公开(公告)日：2015-11-24
申请号：US13821920
申请日：2011-09-16
Applicant: Seiji Hayashi
Inventor： Seiji Hayashi
CPC classification number: H05K1/0219 , H05K1/0216 , H05K1/116 , H05K2201/09236 , H05K2201/093 , H05K2201/09318 , H05K2201/09336 , H05K2201/09663 , H05K2201/0979
Abstract: In a printed wiring board including a first wiring layer and a second wiring layer provided via an insulator layer, at least three guard ground wirings extending along a pair of signal wirings provided in the first wiring layer and supplied with a ground potential are provided between the pair of signal wirings. Thus, crosstalk noise can be reduced without widening a wiring area between the pair of signal wirings.
Abstract translation: 在包括通过绝缘体层提供的第一布线层和第二布线层的印刷布线板中，沿着设置在第一布线层中并提供有接地电位的一对信号布线延伸的至少三个保护接地布线设置在 一对信号线。 因此，可以减小串扰噪声，而不会增加一对信号布线之间的布线面积。
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公开(公告)号：US20150214142A1
公开(公告)日：2015-07-30
申请号：US14590291
申请日：2015-01-06
Applicant: Renesas Electronics Corporation
Inventor： Shuuichi KARIYAZAKI , Ryuichi OIKAWA
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5225 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/0401 , H01L2224/05082 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05644 , H01L2224/05655 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/14135 , H01L2224/16057 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2224/83104 , H01L2924/1517 , H01L2924/15311 , H05K1/0225 , H05K1/0253 , H05K2201/09336 , H05K2201/09681 , H01L2924/014 , H01L2924/00014 , H01L2924/00
Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.
Abstract translation: 为了提高半导体器件的抗噪声性。 半导体器件的布线基板包括形成有信号发送线的第一布线层和与第一布线层的上层或下层相邻地安装的第二布线层。 第二布线层包括在厚度方向上与导线23的一部分重叠的位置处形成开口部的导体平面和安装在导体平面的开口部内的导体图案。 导体图案包括与导体平面隔离的主图案部分（网格图案部分）和耦合主图案部分和导体平面的多个耦合部分。
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公开(公告)号：US08994470B2
公开(公告)日：2015-03-31
申请号：US14113187
申请日：2012-04-25
Applicant: Jun Sakai
Inventor： Jun Sakai
CPC classification number: H01P7/08 , H01P1/20345 , H01P7/082 , H05K1/0225 , H05K1/0243 , H05K1/0253 , H05K1/165 , H05K2201/09263 , H05K2201/09336 , H05K2201/09781
Abstract: A circuit substrate has three wiring layers, wherein a signal line is formed in a first wiring layer; a ground plane is formed in a second wiring layer; a resonant line is formed in a third wiring layer. A circumferential slit is formed in the ground plane, wherein an island electrode separated from the ground plane is formed inside the slit. The left end of the resonant line is connected to the island electrode through an interlayer-connecting via, while the right end of the resonant line is connected to the ground plane through an interlayer-connecting via. A transmission line (or a microstrip line) is formed using the signal line and the ground plane, and therefore a complex resonator is formed to embrace the transmission line. This achieves band elimination with regard to a signal component of a resonance frequency among signals propagating through the microstrip line. Thus, it is possible to form a noise suppression structure without mounting additional parts on the circuit substrate, and therefore it is possible to effectively eliminate power distribution noise and noise propagating through the signal line with a small and simple configuration.
Abstract translation: 电路基板具有三个布线层，其中信号线形成在第一布线层中; 在第二布线层中形成接地平面; 在第三布线层中形成谐振线。 在接地平面内形成有周向狭缝，在狭缝内部形成有与接地面分离的岛状电极。 谐振线路的左端通过层间连接通孔连接到岛状电极，而谐振线路的右端通过层间连接通孔连接到接地层。 使用信号线和接地层形成传输线（或微带线），因此形成复数谐振器以包围传输线。 这实现了通过微带线传播的信号中的谐振频率的信号分量的频带消除。 因此，可以形成噪声抑制结构而不在电路基板上安装附加部件，因此可以以简单的结构有效地消除通过信号线传播的功率分配噪声和噪声。
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