公开(公告)号：US20050003076A1

公开(公告)日：2005-01-06

申请号：US10893938

申请日：2004-07-20

Applicant: Toshiyuki Toyoshima ,  Satoshi Yanaura ,  Yasuo Furuhashi ,  Hirofumi Fujioka

Inventor： Toshiyuki Toyoshima ,  Satoshi Yanaura ,  Yasuo Furuhashi ,  Hirofumi Fujioka

IPC: H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H01L23/02 ,  H05K3/42

CPC classification number: H05K3/4069 ,  H05K3/0023 ,  H05K3/4661 ,  H05K2201/0133 ,  H05K2201/0162 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/09581 ,  H05K2201/096 ,  H05K2203/1461 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Method of producing a multi-layered wiring board comprising the steps of subjecting the photosensitive resin to exposure- and development-treatment to form the holes having a predetermined size and shape; depositing and forming the curable resin to the insulating layer having the holes formed therein in such a manner as to bury the holes, and conducting heat-treatment to form the cured thin film of the curable resin on the surface of the insulating layer; and so removing the curable resin as to leave the cured thin film to obtain the via-holes having the reduced opening size by the cured thin film.

Abstract translation: 制造多层布线板的方法包括以下步骤：对感光树脂进行曝光和显影处理以形成具有预定尺寸和形状的孔; 在形成有孔的绝缘层上沉积和形成固化树脂，以便掩埋孔，进行热处理以在绝缘层的表面上形成固化树脂的固化薄膜; 从而除去固化树脂以留下固化的薄膜，以通过固化的薄膜获得具有减小的开口尺寸的通孔。

公开(公告)号：US20040217455A1

公开(公告)日：2004-11-04

申请号：US10483175

申请日：2004-01-09

Inventor： Osamu Shiono ,  Takao Ishikawa ,  Takashi Namekawa ,  Yasutaka Suzuki ,  Takashi Naito ,  Hiroki Yamamoto ,  Daigoro Kamoto ,  Ken Takahashi ,  Tadanori Segawa ,  Toshiya Sato ,  Takao Miwa ,  Shigehisa Motowaki

IPC: H01L023/02

CPC classification number: H05K3/4061 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49883 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/426 ,  H05K2201/0116 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/09827 ,  H05K2201/09981 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wiring glass substrate includes a glass substrate formed of glass and having a plurality of holes formed at predetermined positions, bumps so formed as to be connected to a conductive material filling the holes and wirings formed on a surface opposite to a surface having the bumps formed thereon and electrically connecting a plurality of connection terminals arranged in intervals different from intervals of the holes to the conductive material. The shape of the conductive material is porous and porous electrodes are bonded to the inner wall surfaces of the holes by an anchor effect to increase the strength of the glass substrate.

Abstract translation: 布线玻璃基板包括由玻璃形成的玻璃基板，在预定位置形成有多个孔，凸起形成为与填充孔的导电材料连接，形成在与形成有凸点的表面相对的表面上的布线 并且将与间隔不同的间隔布置的多个连接端子电连接到导电材料上。 导电材料的形状是多孔的，并且多孔电极通过锚固效应结合到孔的内壁表面，以增加玻璃基底的强度。

公开(公告)号：US20040201367A1

公开(公告)日：2004-10-14

申请号：US10833817

申请日：2004-04-27

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Fumio Echigo ,  Tadashi Nakamura ,  Daizo Andoh

IPC: H02J007/16 ,  H01G004/35

CPC classification number: H05K1/162 ,  H01L28/60 ,  H05K1/141 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09581

Abstract: A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in through holes that pass through the dielectric layer, the power source layer electrode, and the grounding layer electrode, and are insulated by insulation walls from the power source layer electrode and the grounding layer electrode provided inside. The capacitor-connection feedthrough conductors are formed in regions where only either the power source layer electrode or the grounding layer electrode is provided, and are connected electrically with either the power source layer electrode or the grounding layer electrode. This configuration makes the electric connection for employing the capacitors and the electric connection between faces of the sheet independent from each other. Thus, it is possible to provide a capacitor sheet in which the adverse effects of inductances of vias are minimized.

Abstract translation: 电容器片包括层压片，用于电连接层压片的表面的接口连接馈通导体和电容器连接馈通导体。 层叠片具有至少一层由电源层电极，接地层电极和插在电源层电极和接地层电极之间的电介质层构成的层叠体。 界面连接馈通导体形成在穿过电介质层，电源层电极和接地层电极的通孔中，并且由设置在内部的电源层电极和接地层电极的绝缘壁绝缘。 电容器连接馈通导体形成在仅设置电源层电极或接地层电极的区域中，并且与电源层电极或接地层电极电连接。 这种构造使得用于采用电容器的电连接和片材的面之间的电连接彼此独立。 因此，可以提供一种电容器片，其中通孔的电感的不利影响被最小化。

公开(公告)号：US06794729B2

公开(公告)日：2004-09-21

申请号：US10085116

申请日：2002-03-01

Applicant: Toru Mori ,  Takao Yamakazi ,  Koichiro Nakase

Inventor： Toru Mori ,  Takao Yamakazi ,  Koichiro Nakase

IPC: H01L27108

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0306 ,  H05K1/141 ,  H05K3/4053 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09581 ,  H05K2201/10719

Abstract: A stacked capacitor which comprises: a dielectric layer; a two-dimensional array of terminal electrodes on at least one of first and second surfaces of the dielectric layer; first internal electrodes stacked in multi-levels in the dielectric layer, and the first internal electrodes being electrically connected to a power line second internal electrodes stacked in multi-levels in the dielectric layer, and the second internal electrodes being electrically connected to a ground line; vias in the dielectric layer, so that the terminal electrodes being electrically connected through the vias to the first and second internal electrodes.

Abstract translation: 一种叠层电容器，包括：介电层; 电介质层的第一和第二表面中的至少一个上的端子电极的二维阵列; 所述第一内部电极在所述电介质层中堆叠成多层，所述第一内部电极电连接到所述电介质层中以多层叠层的电力线第二内部电极，所述第二内部电极电连接到接地线 ; 电介质层中的通孔，使得端子电极通过通孔电连接到第一和第二内部电极。

公开(公告)号：US06756628B2

公开(公告)日：2004-06-29

申请号：US10155700

申请日：2002-05-24

Applicant: Fumio Echigo ,  Tadashi Nakamura ,  Daizo Andoh

Inventor： Fumio Echigo ,  Tadashi Nakamura ,  Daizo Andoh

IPC: H01L27108

CPC classification number: H05K1/162 ,  H01L28/60 ,  H05K1/141 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09581

Abstract: A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in through holes that pass through the dielectric layer, the power source layer electrode, and the grounding layer electrode, and are insulated by insulation walls from the power source layer electrode and the grounding layer electrode provided inside. The capacitor-connection feedthrough conductors are formed in regions where only either the power source layer electrode or the grounding layer electrode is provided, and are connected electrically with either the power source layer electrode or the grounding layer electrode. This configuration makes the electric connection for employing the capacitors and the electric connection between faces of the sheet independent from each other. Thus, it is possible to provide a capacitor sheet in which the adverse effects of inductances of vias are minimized.

Abstract translation: 电容器片包括层压片，用于电连接层压片的表面的接口连接馈通导体和电容器连接馈通导体。 层叠片具有至少一层由电源层电极，接地层电极和插在电源层电极和接地层电极之间的电介质层构成的层叠体。 界面连接馈通导体形成在穿过电介质层，电源层电极和接地层电极的通孔中，并且由设置在内部的电源层电极和接地层电极的绝缘壁绝缘。 电容器连接馈通导体形成在仅设置电源层电极或接地层电极的区域中，并且与电源层电极或接地层电极电连接。 这种构造使得用于采用电容器的电连接和片材的面之间的电连接彼此独立。 因此，可以提供一种电容器片，其中通孔的电感的不利影响被最小化。

公开(公告)号：US06731004B2

公开(公告)日：2004-05-04

申请号：US09734412

申请日：2000-12-11

Applicant: Kazuto Saitoh

Inventor： Kazuto Saitoh

IPC: H01L2348

CPC classification number: H01L21/486 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/465 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  Y10T29/49128 ,  Y10T29/49156 ,  H01L2924/00

Abstract: An electronic device and method of making same wherein the device includes a substrate (e.g., a printed wiring board or semiconductor chip) having a circuit thereon, a first non-photosensitive layer (e.g., polyimide resin) positioned on the substrate and over the substrate's circuit, a second, photosensitive layer (e.g., epoxy resin) positioned on the first layer, and an electrically conductive layer positioned on the first, non-photosensitive layer and electrically coupled to the circuit through a hole in the first layer.

Abstract translation: 一种电子器件及其制造方法，其中该器件包括其上具有电路的衬底（例如，印刷线路板或半导体芯片），位于衬底上并位于衬底上的第一非感光层（例如，聚酰亚胺树脂） 电路，第二感光层（例如，环氧树脂），以及定位在第一非感光层上的导电层，并通过第一层中的一个孔电耦合到电路。

公开(公告)号：US06714308B2

公开(公告)日：2004-03-30

申请号：US10233772

申请日：2002-09-03

Applicant: Christopher James Evans ,  Michael Küchel

Inventor： Christopher James Evans ,  Michael Küchel

IPC: G01B902

CPC classification number: H05K1/024 ,  G01B11/2441 ,  G01B11/255 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/445 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K2201/09581 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Interferometric apparatus and methods by which aspheric surfaces and wavefronts may be precisely measured. The apparatus is provided with two modes of operation. In one mode, the apparatus is configured generally as a Fizeau interferometer in which an aspheric reference surface is used to permit the rapid, robust measurement of the difference between the aspheric reference surface and an aspheric test optic or wavefront. In another mode of operation, the aspheric test surface itself is completely characterized through in-situ use of an interferometric scanning technique using a spherical reference surface.

Abstract translation: 可以精确测量非球面和波前的干涉仪和方法。 该装置具有两种操作模式。 在一种模式中，该装置通常配置为Fizeau干涉仪，其中使用非球面参考表面来快速，鲁棒地测量非球面参考表面和非球面测试光学元件或波前之间的差异。 在另一种操作模式中，通过使用球面参考表面的干涉扫描技术的原位使用，非球面测试表面本身完全表征。

公开(公告)号：US06629367B2

公开(公告)日：2003-10-07

申请号：US09730959

申请日：2000-12-06

Applicant: Jeremy W. Burdon ,  Ross A. Miesem ,  Chowdary Ramesh Koripella

Inventor： Jeremy W. Burdon ,  Ross A. Miesem ,  Chowdary Ramesh Koripella

IPC: H05K342

CPC classification number: H05K3/4061 ,  H01L21/486 ,  H05K1/0306 ,  H05K2201/09581 ,  H05K2201/09809 ,  Y10T29/49083 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for forming an electrically isolated via in a multilayer ceramic package and an electrical connection formed within the via are disclosed. The method includes punching a first via in a first layer, filling the first via with a cross-linkable paste, curing the paste to form an electrical insulator precursor and forming the via in the insulator precursor. The electrical connection formed includes an insulator made from a cross-linked paste supported by a substrate of a multilayer ceramic package and a conductive connection supported by the insulator.

Abstract translation: 公开了一种在多层陶瓷封装中形成电隔离通孔的方法和形成在通孔内的电连接。 该方法包括在第一层中冲压第一通孔，用可交联的浆料填充第一通孔，固化糊料以形成电绝缘体前体并在绝缘体前体中形成通孔。 形成的电连接包括由多层陶瓷封装的衬底支撑的交联膏和由绝缘体支撑的导电连接器制成的绝缘体。

公开(公告)号：US06518515B2

公开(公告)日：2003-02-11

申请号：US09976376

申请日：2001-10-12

Applicant: Toshihiro Nishii ,  Shigeru Yamane ,  Shinji Nakamura ,  Hidenori Hayashi ,  Toru Fujimoto ,  Toshiharu Okada ,  Izuru Nakai

Inventor： Toshihiro Nishii ,  Shigeru Yamane ,  Shinji Nakamura ,  Hidenori Hayashi ,  Toru Fujimoto ,  Toshiharu Okada ,  Izuru Nakai

IPC: H01R909

CPC classification number: H05K3/4069 ,  H05K1/0366 ,  H05K3/0032 ,  H05K2201/0278 ,  H05K2201/0355 ,  H05K2201/09581 ,  H05K2203/1136 ,  H05K2203/1461 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/249953 ,  Y10T428/249996

Abstract: In manufacturing a double-layered or a multi-layered printed wiring board, a layer of metamorphic substance, which is created by transmuting a substrate material, is formed on an inner wall of a hole during a perforation process of the substrate utilizing radiation energy. The layer of metamorphic substance prevents conductive materials constituting electrical connection formed on the inner wall of the hole from dispersing over a surface of the substrate or permeating into the substrate.

Abstract translation: 在制造双层或多层印刷线路板的过程中，利用辐射能在衬底的穿孔过程中，在孔的内壁上形成通过变换衬底材料产生的变质物质层。 变质物质层防止形成在孔的内壁上的导电材料在衬底的表面上分散或渗透到衬底中。

公开(公告)号：US06501031B1

公开(公告)日：2002-12-31

申请号：US09655809

申请日：2000-09-06

Applicant: Andrew Z. Glovatsky ,  Jay D. Baker ,  Robert Edward Belke ,  Myron Lemecha ,  Richard Keith McMillan ,  Thomas B. Krautheim

Inventor： Andrew Z. Glovatsky ,  Jay D. Baker ,  Robert Edward Belke ,  Myron Lemecha ,  Richard Keith McMillan ,  Thomas B. Krautheim

IPC: H05K111

CPC classification number: H05K3/445 ,  H05K3/386 ,  H05K3/4038 ,  H05K3/4092 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2201/09581 ,  H05K2203/1438 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49172

Abstract: A multi-layer electronic circuit board design 10 having a core member 12, a pair of dielectric layers 14, 16 disposed thereon, and a first circuit portion 20 which is coupled to the dielectric layer 14 and core member 12 using a layer of adhesive material 18. Circuit board design 10 further having selectively formed “blind” apertures, vias or cavities 22 formed through the first circuit portion 20, dielectric layer 14, and adhesive layer 18, thereby exposing core member 12.

Abstract translation: 具有芯构件12，设置在其上的一对电介质层14,16的多层电子电路板设计10以及使用粘合材料层连接到电介质层14和芯构件12的第一电路部分20 电路板设计10还具有选择性地形成通过第一电路部分20形成的“盲”孔，通孔或空腔22，电介质层14和粘合层18，从而露出芯构件12。