公开(公告)号：US20050237126A1

公开(公告)日：2005-10-27

申请号：US10832677

申请日：2004-04-27

Applicant: Samuel Babb ,  Erik Swanson ,  Lowell Kolb

Inventor： Samuel Babb ,  Erik Swanson ,  Lowell Kolb

IPC: H01P3/08 ,  H01P5/02 ,  H05K1/00 ,  H05K1/02

CPC classification number: H05K1/0216 ,  H01P3/08 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09727

Abstract: A printed wiring board comprises a first plane having a split formed therein and at least one signal trace disposed on a second plane. The signal trace comprises an increased width in an area of the second plane corresponding to a location of the split.

Abstract translation: 印刷电路板包括其中形成有分裂的第一平面和设置在第二平面上的至少一个信号迹线。 信号迹线包括对应于分割位置的第二平面区域中增加的宽度。

公开(公告)号：US06941649B2

公开(公告)日：2005-09-13

申请号：US10068745

申请日：2002-02-05

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H05K3/02

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

Abstract translation: 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。

公开(公告)号：US20050195554A1

公开(公告)日：2005-09-08

申请号：US11060109

申请日：2005-02-17

Applicant: William Borland ,  Xin Fang

Inventor： William Borland ,  Xin Fang

IPC: H01G4/01 ,  H01G4/255 ,  H05K1/09 ,  H05K1/16 ,  H05K3/22 ,  H05K3/42 ,  H05K3/46 ,  H01G4/005

CPC classification number: H01G4/01 ,  H01G4/255 ,  H05K1/092 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2203/107 ,  H05K2203/171 ,  H05K2203/175

Abstract: In a printed wiring board, capacitors have electrode layers that may be selectively trimmed to obtain high tolerances. The electrode layers can be formed from a plurality of elongated electrode portions, each of which can be selectively trimmed. The electrode layers can also be formed from interdigitated elongated electrode portions.

Abstract translation: 在印刷电路板中，电容器具有可以选择性地修整以获得高公差的电极层。 电极层可以由多个细长电极部分形成，每个细长电极部分可以选择性地修整。 电极层也可以由叉指的细长电极部分形成。

公开(公告)号：US20050178583A1

公开(公告)日：2005-08-18

申请号：US10843466

申请日：2004-05-12

Applicant: Sheng-Yuan Lee

Inventor： Sheng-Yuan Lee

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0253 ,  H05K1/0262 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969

Abstract: A structure of a circuit board for improving the performance of routing traces is described as eliminating the resonant effects from the inner layers in a circuit board. For eliminating the stray capacitor effect between the planes in the circuit board, the present invention uses a method for etching an area of a power plane and the area is corresponding to a routing plane. Consequently, the routing trace can make good electric potential reference of a ground plane. Due to the reduction of the stray capacitor, the structure for improving the performance of routing traces of the invention can avoid the resonance effect and parasitic resonance in the circuit board as produced in a high-frequency situation in order to promote the quality of the circuit board.

Abstract translation: 描述了用于提高布线迹线性能的电路板的结构，以消除电路板内层的谐振效应。 为了消除电路板中的平面之间的杂散电容器效应，本发明使用蚀刻电源平面区域的方法，并且该区域对应于布线平面。 因此，路由跟踪可以使接地层具有良好的电位参考。 由于杂散电容器的减少，用于提高本发明的布线迹线性能的结构可以避免在高频情况下产生的电路板中的谐振效应和寄生谐振，以便提高电路的质量 板。

公开(公告)号：US06887738B2

公开(公告)日：2005-05-03

申请号：US10293441

申请日：2002-11-14

Applicant: Susumu Shintani

Inventor： Susumu Shintani

IPC: H01L21/60 ,  H01L23/498 ,  H05K1/11 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L24/16 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/1607 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/14 ,  H05K1/111 ,  H05K1/113 ,  H05K2201/09381 ,  H05K2201/09427 ,  H05K2201/09663 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device is arranged such that a semiconductor chip having electrodes is flip chip mounted on printed substrate pads on a printed wiring substrate by a bump formed on each electrode. The semiconductor chip and the printed wiring substrate are fixed with a thermo-setting resin. A penetration hole is formed within an area where the printed substrate pad contacts each gold bump, and the gold bump has a joint section also on a side face of the penetration hole of the printed substrate pad. With this structure, the semiconductor device has a secure electrical connection between the bump and the metal pattern.

Abstract translation: 半导体器件被布置成使得具有电极的半导体芯片通过在每个电极上形成的凸块倒装在印刷布线基板上的印刷基板上。 半导体芯片和印刷布线基板用热固性树脂固定。 在印刷基板焊盘与每个金凸块接触的区域内形成贯通孔，并且金凸块也在印刷基板焊盘的贯通孔的侧面上具有接合部分。 利用这种结构，半导体器件在凸起和金属图案之间具有牢固的电连接。

公开(公告)号：US20050087841A1

公开(公告)日：2005-04-28

申请号：US10684812

申请日：2003-10-15

Applicant: Koki Ishizaki ,  Takeshi Shirato

Inventor： Koki Ishizaki ,  Takeshi Shirato

IPC: H01C17/242 ,  H05K1/09 ,  H05K1/16 ,  H05K3/28 ,  H05K3/46 ,  H01L29/00

CPC classification number: H01C17/242 ,  H05K1/092 ,  H05K1/167 ,  H05K3/4644 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/107 ,  H05K2203/171

Abstract: A multilayer electronic substrate is manufactured by employed: a first conductor layer arranged on an insulating substrate; an insulator arranged on the first conductor layer; a resistor arranged on the insulator; and second conductor layers for sandwiching the resistor to be connected to this resistor. In this multilayer electronic substrate, the resistor is trimmed so as to adjust an electric characteristic of a circuit, and a portion of the first conductor layer, which corresponds to a trimming portion of the resistor, is constituted by a first insulating region.

Abstract translation: 制造多层电子基板，其特征在于，采用：设置在绝缘基板上的第一导体层; 布置在所述第一导体层上的绝缘体; 布置在绝缘体上的电阻器; 以及用于夹持要连接到该电阻器的电阻器的第二导体层。 在该多层电子基板中，对电阻进行修整以调整电路的电特性，并且与电阻器的修整部对应的第一导体层的一部分由第一绝缘区域构成。

公开(公告)号：US20050078415A1

公开(公告)日：2005-04-14

申请号：US10964224

申请日：2004-10-13

Applicant: Tatsumi Tsuchiya ,  Yuhsuke Matsumoto ,  Takaaki Murokawa ,  Naoki Fujii ,  Takuya Satoh ,  Yasuhiro Mita ,  Hiroyasu Tsuchida ,  Yoshio Uematsu

Inventor： Tatsumi Tsuchiya ,  Yuhsuke Matsumoto ,  Takaaki Murokawa ,  Naoki Fujii ,  Takuya Satoh ,  Yasuhiro Mita ,  Hiroyasu Tsuchida ,  Yoshio Uematsu

IPC: G11B5/60 ,  G11B5/48 ,  G11B21/21 ,  H05K1/18 ,  H05K3/34

CPC classification number: G11B5/4853 ,  G11B5/484 ,  G11B5/486 ,  H01L2224/742 ,  H05K1/189 ,  H05K3/3442 ,  H05K3/3494 ,  H05K2201/0397 ,  H05K2201/09663 ,  H05K2201/09745 ,  H05K2203/041 ,  H05K2203/107 ,  H05K2203/159 ,  Y02P70/613 ,  Y10T29/49025 ,  Y10T29/4903 ,  Y10T29/49032 ,  Y10T29/49046 ,  Y10T29/49144 ,  Y10T29/49179

Abstract: An integrated lead suspension includes a solder ball that is placed between a lead wiring pad provided on a flexure of the suspension, and a bonding pad provided on a slider of a head gimbal section. The lead wiring pad and bonding pad are soldered by melting the solder ball. As a result, there is provided a recessed section into which a solder ball is placed by way of surface raised sections, using gravitational force, in the vicinity of the center line of the surface of the lead wiring pad. In this way the position of the solder ball is not displaced from the center line when a bonding pad and lead wiring pad are connected by means of a solder ball.

公开(公告)号：US20050063135A1

公开(公告)日：2005-03-24

申请号：US10664638

申请日：2003-09-18

Applicant: William Borland ,  Xin Fang

Inventor： William Borland ,  Xin Fang

IPC: H01G4/01 ,  H01G4/255 ,  H05K1/09 ,  H05K1/16 ,  H05K3/22 ,  H05K3/42 ,  H05K3/46 ,  H01G4/005

CPC classification number: H01G4/01 ,  H01G4/255 ,  H05K1/092 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2203/107 ,  H05K2203/171 ,  H05K2203/175

Abstract: In a printed wiring board, capacitors have electrode layers that may be selectively trimmed to obtain high tolerances. The electrode layers can be formed from a plurality of elongated electrode portions, each of which can be selectively trimmed. The electrode layers can also be formed from interdigitated elongated electrode portions.

公开(公告)号：US06864434B2

公开(公告)日：2005-03-08

申请号：US10441647

申请日：2003-05-19

Applicant: Chin-Huang Chang ,  Chin-Tien Chiu ,  Chung-Lun Liu

Inventor： Chin-Huang Chang ,  Chin-Tien Chiu ,  Chung-Lun Liu

IPC: H01L23/498 ,  H05K1/02 ,  H05K3/28 ,  H05K1/03

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/28 ,  H05K2201/09663 ,  H05K2201/09781 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/4916 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A warpage-preventive circuit board and method for fabricating the same is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

Abstract translation: 提供了一种防翘曲电路板及其制造方法，其中在电绝缘芯层的表面上形成多个导电迹线，并且多个不连续的虚设电路区域设置在电气绝缘电路板的表面上 - 绝缘芯层在没有导电迹线的区域处，其中相邻的虚设电路区域至少间隔开。 在高温制造过程中，虚拟电路区域有助于降低热应力，并且汲取吸收虚拟电路区域的热膨胀，从而防止电路板翘曲和安装在电路板上的芯片的裂纹，使得屈服 并且可以提高制造的半导体器件的可靠性。

公开(公告)号：US20050023683A1

公开(公告)日：2005-02-03

申请号：US10877733

申请日：2004-06-25

Applicant: Myung-Kee Chung ,  Min-Keun Kwak ,  Kil-Soo Kim

Inventor： Myung-Kee Chung ,  Min-Keun Kwak ,  Kil-Soo Kim

IPC: H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/11 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L2224/81385 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09663 ,  H05K2201/09809 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A semiconductor package has ball lands each configured to have a composite structure of SMD type and NSMD type. One peripheral portion of the ball land is covered with a mask layer, thus forming the SMD type, whereas the other peripheral portion is exposed through an opening area of the mask layer, thus forming the NSMD type. In one embodiment, the first peripheral portion is disposed to face a central point of a ball-mounting surface of a substrate, and the second peripheral portion is disposed to face the opposite direction to the central point. The composite structure of the ball lands provides more stable and enhanced connections between connection balls, such as solder balls, and the ball-mounting surface.

Abstract translation: 半导体封装具有各自被配置为具有SMD型和NSMD型的复合结构的球形焊盘。 球面的一个周边部分被掩模层覆盖，从而形成SMD型，而另一个周边部分通过掩模层的开口区域露出，从而形成NSMD型。 在一个实施例中，第一周边部分设置成面对基板的球安装表面的中心点，并且第二周边部分设置成面向与中心点相反的方向。 球面的复合结构在连接球（例如焊球）和球安装表面之间提供更稳定和增强的连接。