公开(公告)号：US10018599B2

公开(公告)日：2018-07-10

申请号：US14562955

申请日：2014-12-08

Applicant: CANON KABUSHIKI KAISHA

Inventor： Shinan Wang ,  Shinichiro Watanabe

IPC: B81B3/00 ,  B06B1/02 ,  B81C1/00 ,  G01N29/24 ,  G01N29/44 ,  G01N29/06 ,  B81B7/00

CPC classification number: G01N29/2418 ,  B06B1/0292 ,  B81B7/0006 ,  B81B2201/0271 ,  B81B2203/0127 ,  B81B2203/04 ,  B81B2207/07 ,  G01N29/0654 ,  G01N29/2406

Abstract: The present inventions provide a capacitive transducer that can reduce film damage on a substrate surface on a vibration film side due to a difference in thermal expansion coefficient between a through wiring and a substrate and a method of manufacturing the same. The capacitive transducer consists of a plurality of cells with each cell comprising a first electrode and a vibration film on a first surface side of a substrate having a through wiring that penetrates the substrate from a first surface to a second surface of the substrate, the vibration film including a second electrode that is formed with a gap from the first electrode. A holding member that holds a leading end of the through wiring is provided on the first surface side of the substrate.

公开(公告)号：US20180065844A1

公开(公告)日：2018-03-08

申请号：US15698597

申请日：2017-09-07

Applicant: The Government of the United States of America, as Represented by the Secretary of the Navy

Inventor： Eugene A. IMHOFF ,  Francis J. KUB ,  Karl D. HOBART ,  Rachael L. MYERS-WARD

IPC: B81C1/00

CPC classification number: B81C1/00619 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0271 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2203/0127 ,  B81C2201/0112

Abstract: Material structures and methods for etching hexagonal, single-crystal silicon carbide (SiC) materials are provided, which include selection of on-axis or near on-axis hexagonal single-crystal SiC material as the material to be etched. The methods include etching of SiC bulk substrate material, etching of SiC material layers bonded to a silicon oxide layer, etching of suspended SiC material layers, and etching of a SiC material layer anodically bonded to a glass layer. Plasma-etched hexagonal single-crystal SiC materials of the invention may be used to form structures that include, but are not limited to, microelectromechanical beams, microelectromechanical membranes, microelectromechanical cantilevers, microelectromechanical bridges, and microelectromechanical field effect transistor devices. The material structures and methods of the invention beneficially provide improved etch symmetry, improved etch straightness, improved sidewall straightness, improved sidewall smoothness, and reduced sidewall wander compared to etched four degree off-axis SiC materials.

公开(公告)号：US20180009654A1

公开(公告)日：2018-01-11

申请号：US15711890

申请日：2017-09-21

Applicant: InvenSense, Inc.

Inventor： Peter SMEYS ,  Martin LIM

IPC: B81B7/00

CPC classification number: B81B7/007 ,  B81B2201/0207 ,  B81B2201/0214 ,  B81B2201/0228 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2203/0315 ,  B81B2207/012 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A sensor chip includes a first substrate with a first surface and a second surface including at least one CMOS circuit, a first MEMS substrate with a first surface and a second surface on opposing sides of the first MEMS substrate, a second substrate, a second MEMS substrate, and a third substrate including at least one CMOS circuit. The first surface of the first substrate is attached to a packaging substrate and the second surface of the first substrate is attached to the first surface of the first MEMS substrate. The second surface of the first MEMS substrate is attached to the second substrate. The first substrate, the first MEMS substrate, the second substrate and the packaging substrate are provided with electrical inter-connects.

公开(公告)号：US09834434B2

公开(公告)日：2017-12-05

申请号：US14524170

申请日：2014-10-27

Applicant: CANON KABUSHIKI KAISHA

Inventor： Kazuhiko Kato

IPC: B81B7/00 ,  B06B1/02 ,  B81B3/00 ,  B81C1/00

CPC classification number: B81B7/0041 ,  B06B1/0292 ,  B81B3/0021 ,  B81B2201/0271 ,  B81C1/00182 ,  B81C2203/0145

Abstract: Provided are a capacitive transducer that can make a sealing film thickness necessary to seal a gap smaller and can enhance performance such as a wider bandwidth, and a method of manufacturing the capacitive transducer. The capacitive transducer including cells each including a vibration film including a second electrode that is provided with a gap from a first electrode can be manufactured in the following manufacturing method. A convex part is formed on the first electrode, a sacrifice layer having a thickness larger than the thickness of the convex part is formed on the first electrode and the convex part, and a membrane is formed on the sacrifice layer. Further, an etching hole is formed in the membrane at a position above the convex part, the sacrifice layer is etched through the etching hole, and the etching hole is sealed by a sealing layer.

公开(公告)号：US09828236B2

公开(公告)日：2017-11-28

申请号：US14370110

申请日：2013-01-23

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Peter Dirksen ,  Ruediger Mauczok ,  Koray Karakaya ,  Johan Klootwijk ,  Bout Marcelis ,  Marcel Mulder

IPC: H01L29/84 ,  B81B3/00 ,  B06B1/02 ,  B81C1/00 ,  H04R19/00 ,  H04R31/00

CPC classification number: B81B3/0086 ,  B06B1/0292 ,  B81B3/0027 ,  B81B2201/0271 ,  B81C1/00523 ,  H04R19/005 ,  H04R31/00 ,  H04R31/003

Abstract: The present invention relates to a method of manufacturing a capacitive micro- machined transducer (100), in particular a CMUT, the method comprising depositing a first electrode layer (10) on a substrate (1), depositing a first dielectric film (20) on the first electrode layer (10), depositing a sacrificial layer (30) on the first dielectric film (20), the sacrificial layer (30) being removable for forming a cavity (35) of the transducer, depositing a second dielectric film (40) on the sacrificial layer (30), depositing a second electrode layer (50) on the second dielectric film (40), and patterning at least one of the deposited layers and films (10, 20, 30, 40, 50), wherein the depositing steps are performed by Atomic Layer Deposition. The present invention further relates to a capacitive micro-machined transducer (100), in particular a CMUT, manufactured by such method.

公开(公告)号：US20170302004A1

公开(公告)日：2017-10-19

申请号：US15485069

申请日：2017-04-11

Applicant: Kymeta Corporation

Inventor： Ryan Stevenson ,  Kianoush Naeli ,  Mohsen Sazegar ,  Benjamin Sikes ,  Timothy Mason ,  Erik Shipton ,  Nathan Kundtz

IPC: H01Q21/06 ,  H01Q21/00 ,  H01Q3/44 ,  H01Q21/30 ,  H01Q3/26

CPC classification number: H01Q21/065 ,  B81B3/0086 ,  B81B2201/0221 ,  B81B2201/0271 ,  B81B2203/0127 ,  B81B2203/04 ,  B81C1/00158 ,  B81C2203/0118 ,  H01G5/011 ,  H01G5/16 ,  H01G5/18 ,  H01Q3/2676 ,  H01Q3/44 ,  H01Q7/005 ,  H01Q9/0457 ,  H01Q13/103 ,  H01Q21/0031 ,  H01Q21/0087 ,  H01Q21/30 ,  H03J3/02

Abstract: An antenna having radio-frequency (RF) resonators and methods for fabricating the same are described. In one embodiment, the antenna comprises a physical antenna aperture having an array of antenna elements, where the array of antenna elements includes a plurality of radio-frequency (RF) resonators, with each RF resonator of the plurality of RF resonators having an RF radiating element with a microelectromchanical systems (MEMS) device.

公开(公告)号：US20170297896A1

公开(公告)日：2017-10-19

申请号：US15291374

申请日：2016-10-12

Applicant: Robert Bosch GmbH

Inventor： Andrew Graham ,  Gary Yama ,  Gary O'Brien

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81B2201/0271 ,  B81B2203/04 ,  B81B2203/053 ,  B81C1/00095 ,  B81C1/00166 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/0177 ,  B81C2203/0136

Abstract: A device with an out-of-plane electrode includes a device layer positioned above a handle layer, a first electrode defined within the device layer, a cap layer having a first cap layer portion spaced apart from an upper surface of the device layer by a gap, and having an etch stop perimeter defining portion defining a lateral edge of the gap, and an out-of-plane electrode defined within the first cap layer portion by a spacer.

公开(公告)号：US20170291811A1

公开(公告)日：2017-10-12

申请号：US15508130

申请日：2015-09-04

Applicant: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Mohammad YOUNIS

IPC: B81B7/00 ,  G01P15/125 ,  G02B26/08

CPC classification number: B81B7/008 ,  B81B2201/0235 ,  B81B2201/0271 ,  B81B2201/042 ,  G01P15/125 ,  G01P2015/0862 ,  G02B26/0833 ,  H03H3/0076 ,  H03H9/02259 ,  H03H9/02393 ,  H03H9/467 ,  H03H9/525

Abstract: Embodiments of multi-frequency excitation are described. In various embodiments, a natural frequency of a device may be determined. In turn, a first voltage amplitude and first fixed frequency of a first source of excitation can be selected for the device based on the natural frequency. Additionally, a second voltage amplitude of a second source of excitation can be selected for the device, and the first and second sources of excitation can be applied to the device. After applying the first and second sources of excitation, a frequency of the second source of excitation can be swept. Using the methods of multi-frequency excitation described herein, new operating frequencies, operating frequency ranges, resonance frequencies, resonance frequency ranges, and/or resonance responses can be achieved for devices and systems.

公开(公告)号：US09783408B2

公开(公告)日：2017-10-10

申请号：US14307512

申请日：2014-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bang-Chiang Lan ,  Ming-I Wang ,  Li-Hsun Ho ,  Hui-Min Wu ,  Min Chen ,  Chien-Hsin Huang

IPC: H04R7/00 ,  B81B3/00 ,  H04R19/00 ,  H04R31/00 ,  H04R3/00

CPC classification number: B81B3/0021 ,  B81B2201/0271 ,  H04R3/00 ,  H04R7/00 ,  H04R19/005 ,  H04R31/00 ,  H04R2499/11 ,  Y10T29/49002

Abstract: A structure of micro-electro-mechanical systems (MEMS) electroacoustic transducer is disclosed. The MEMS electroacoustic transducer includes a substrate having a MEMS device region, a diaphragm having openings and disposed in the MEMS device region, a silicon material layer disposed on the diaphragm and sealing the diaphragm, and a conductive pattern disposed beneath the diaphragm in the MEMS device region. Preferably, a first cavity is also formed between the diaphragm and the substrate.

公开(公告)号：US20170217766A1

公开(公告)日：2017-08-03

申请号：US15484765

申请日：2017-04-11

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.