公开(公告)号：US07351915B2

公开(公告)日：2008-04-01

申请号：US10999442

申请日：2004-11-29

Applicant: Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

Inventor： Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/1218 ,  H01G4/248 ,  H01G4/33 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1366 ,  Y10T29/42

Abstract: A printed circuit board (PCB) having at least one embedded capacitor and a method of fabricating the same is provided. A dielectric layer is formed using a ceramic material having a high capacitance, thereby assuring that the capacitors each have a high dielectric constant corresponding to the capacitance of a decoupling chip capacitor.

Abstract translation: 提供了具有至少一个嵌入式电容器的印刷电路板（PCB）及其制造方法。 使用具有高电容的陶瓷材料形成电介质层，从而确保电容器各自具有对应于去耦芯片电容器的电容的高介电常数。

公开(公告)号：US07351657B2

公开(公告)日：2008-04-01

申请号：US11150450

申请日：2005-06-10

Applicant: David A. Barnes ,  Jason C. Grooms ,  Neal B. Martinez ,  Joseph M. McKinnerney

Inventor： David A. Barnes ,  Jason C. Grooms ,  Neal B. Martinez ,  Joseph M. McKinnerney

IPC: H01L21/44

CPC classification number: H01L23/3128 ,  H01L21/4853 ,  H01L21/4864 ,  H01L23/3135 ,  H01L2924/00013 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/0179 ,  H05K2203/025 ,  H05K2203/0557 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A method and apparatus are disclosed for selective removal of a conformal coating from the solder balls of grid array packages such that the benefits of the coating are realized. An ancillary benefit of the invention is improved process-ability of the grid array package by improving the mechanical containment of the solder during the reflow process and improved electrical isolation between the individual solder attachment points. For example, a method for coating a ball grid array is provided, which includes coating the ball grid array with a thin layer of parylene. Next, the solder ball side of the part is butter smeared or squeegeed with a water soluble coating and assembled wet. A mask having holes in the same pattern as the balls in the grid, and a thickness that is about 80% of the height of the balls, is applied to the solder ball side of the part. This side of the part is then butter smeared again with the water soluble coating, and the entire assembly is allowed to dry. At this point, about 20% of each parylene-coated solder ball protrudes higher than the surface of the mask. The solder ball side of the part is then grit blasted with an abrasive material. The extent that the abrasive material removes the parylene coating from the solder balls is limited by the mask and the layer of water soluble coating. Therefore, the grit blasting removes the parylene coating from only the protruding areas (e.g., about top 20%) of the solder balls. Water is then used to remove the water soluble coating, and the parylene coated part is baked to remove moisture. Thus, a parylene coated ball grid array (or column grid array) is provided that is highly impervious to moisture, has a very high dielectric strength, and thereby improves the electrical performance and reliability of the surface mounted part.

Abstract translation: 公开了一种用于从栅格阵列封装的焊球选择性地去除保形涂层的方法和装置，从而实现了涂层的优点。 本发明的辅助优点是通过改善在回流过程期间焊料的机械容纳以及改善各个焊接附着点之间的电隔离来提高栅格阵列封装的工艺能力。 例如，提供了一种用于涂覆球栅阵列的方法，其包括用聚对二甲苯的薄层涂覆球栅阵列。 接下来，部件的焊球侧面被黄油涂抹或用水溶性涂层刮擦并组装湿。 具有与网格中的球相同的图案的孔和厚度为球的高度的约80％的掩模施加到部件的焊球侧。 然后将该部分的这一面用水溶性涂层再涂抹，并使整个组件干燥。 此时，每个聚对二甲苯涂覆的焊球的约20％比掩模的表面高。 然后用研磨材料对部件的焊球侧进行喷砂处理。 研磨材料从焊球去除聚对二甲苯涂层的程度受到掩模和水溶性涂层的限制。 因此，喷砂仅从焊球的突出区域（例如，约20％左右）去除聚对二甲苯涂层。 然后使用水去除水溶性涂层，并烘烤聚对二甲苯涂布部分以除去水分。 因此，提供了高度不透水分的聚对二甲苯涂覆的球栅阵列（或列格栅阵列），具有非常高的介电强度，从而提高了表面安装部件的电性能和可靠性。

公开(公告)号：US20080044672A1

公开(公告)日：2008-02-21

申请号：US11923594

申请日：2007-10-24

Applicant: William Borland ,  Ian Burn ,  Jon Ihlefeld ,  Jon-Paul Maria ,  Seigi Suh

Inventor： William Borland ,  Ian Burn ,  Jon Ihlefeld ,  Jon-Paul Maria ,  Seigi Suh

IPC: B32B15/01

CPC classification number: H01L21/02197 ,  C01G23/006 ,  C01P2004/82 ,  C01P2006/40 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02337 ,  H01L21/31691 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  Y10T29/417 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T428/31678

Abstract: The present invention is directed to an article comprising a dielectric layer formed from any solution composition that can form barium titanate during firing and containing manganese in an amount between 0.002 and 0.05 atom percent of the solution composition, wherein the dielectric layer has been formed on metal foil and fired in a reducing atmosphere.

Abstract translation: 本发明涉及一种制品，其包括由任意的溶液组合物形成的介电层，所述溶液组合物可在焙烧期间形成钛酸钡并且含有0.002至0.05原子％的溶液组合物中的锰，其中介电层已形成于金属 在还原气氛中进行烫伤。

公开(公告)号：US07326643B2

公开(公告)日：2008-02-05

申请号：US11808596

申请日：2007-06-12

Applicant: Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

Inventor： Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

IPC: H01L21/4751

CPC classification number: G11C11/22 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/16 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/0401

Abstract: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.

Abstract translation: 一种制造电路化衬底的方法，所述电路化衬底由其上具有导电图案的至少一种电介质材料组成。 图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成 设备。

公开(公告)号：US20070294888A1

公开(公告)日：2007-12-27

申请号：US11895355

申请日：2007-08-24

Applicant: Ronald Whittaker ,  Joe Guerra ,  Ciprian Marcoci

Inventor： Ronald Whittaker ,  Joe Guerra ,  Ciprian Marcoci

IPC: H05K3/42

CPC classification number: H01F27/266 ,  H01F17/0033 ,  H01F17/062 ,  H01F19/04 ,  H01F27/2804 ,  H01F41/046 ,  H01F2017/002 ,  H05K1/165 ,  H05K1/189 ,  H05K3/389 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/09809 ,  H05K2201/10416 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Electrical connection between the plural levels of circuitry and multiple windings around magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.

Abstract translation: 微型电路和电感器部件，其中在支撑面板的每一侧，通常是印刷电路板或刚性柔性件上形成多层印刷电路。 多层电路和磁性构件周围的多个绕组之间的电连接由多个电镀通孔导体提供。 小的通孔开口容纳多个电镀通孔导体，因为它们通过非常薄的真空沉积的有机层（例如具有高介电强度的聚对二甲苯）绝缘。 通过首先在有机层的表面上施加粘合剂促进剂，然后真空沉积有机层，来提供该镀铜的有机层的附着力。

公开(公告)号：US20070249089A1

公开(公告)日：2007-10-25

申请号：US11808596

申请日：2007-06-12

Applicant: Subahu Desai ,  How Lin ,  John Lauffer ,  Voya Markovich ,  David Thomas

Inventor： Subahu Desai ,  How Lin ,  John Lauffer ,  Voya Markovich ,  David Thomas

IPC: H01L51/40

CPC classification number: G11C11/22 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/16 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/0401

Abstract: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.

Abstract translation: 一种制造电路化衬底的方法，所述电路化衬底由其上具有导电图案的至少一种电介质材料组成。 图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成 设备。

公开(公告)号：US20070240901A1

公开(公告)日：2007-10-18

申请号：US11812124

申请日：2007-06-15

Applicant: Keishiro Okamoto ,  Tomoyuki Abe ,  Motoaki Tani ,  Nobuyuki Hayashi

Inventor： Keishiro Okamoto ,  Tomoyuki Abe ,  Motoaki Tani ,  Nobuyuki Hayashi

IPC: H05K1/11

CPC classification number: H05K3/445 ,  H05K1/056 ,  H05K3/426 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/09581 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The wiring board comprises a plate-shaped conductive core material 10 with a through-hole 12 formed in, an insulation layer 14 formed on the surface of the conductive core material 10 and on the inside wall of the through-hole 12, a resin 18 buried in the through-hole 12 with the insulation layer 14 formed in, wirings 22a, 22b formed on the upper surface and the undersurface of the conductive core material 10 with the insulation layer 14 formed on, and an wiring 22d formed in the through-hole 20 formed in the resin 18 and electrically connected to the wirings 22a, 22b.

Abstract translation: 布线板包括具有形成在其中的通孔12的板状导电芯材10，形成在导电芯材10的表面上的绝缘层14和通孔12的内壁上的树脂18 埋置在通孔12中，其中形成有绝缘层14，形成在形成有绝缘层14的导电芯材10的上表面和下表面上的布线22a，22b以及形成在其中的布线22d 通孔20形成在树脂18中并电连接到布线22a，22b。

公开(公告)号：US20070234539A1

公开(公告)日：2007-10-11

申请号：US11730979

申请日：2007-04-05

Applicant: Seung Eun Lee ,  Yul Kyo Chung ,  Hyung Dong Kang ,  Hyun Ju Jin

Inventor： Seung Eun Lee ,  Yul Kyo Chung ,  Hyung Dong Kang ,  Hyun Ju Jin

IPC: H04R17/00 ,  H01L21/8242

CPC classification number: H04R19/00 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0346 ,  H05K2203/0353 ,  Y10T29/417 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/435

Abstract: A method for manufacturing a capacitor embedded in a PCB includes: preparing a copper clad lamination (CCL) substrate having a reinforcement member and copper foils formed on both surfaces of the reinforcement member; planarizing surfaces of the copper foils of the CCL substrate; forming a dielectric layer on the planarized surface of the copper foils; and forming a top electrode on the dielectric layer.

Abstract translation: 一种嵌入在PCB中的电容器的制造方法，其特征在于，包括：具有加强部件的铜包覆层叠（CCL）基板和形成在所述加强部件的两面的铜箔; 平坦化CCL基板的铜箔表面; 在铜箔的平坦化表面上形成电介质层; 并在电介质层上形成顶部电极。

公开(公告)号：US20070209201A1

公开(公告)日：2007-09-13

申请号：US11736408

申请日：2007-04-17

Applicant: Ivoyl Koutsaroff ,  Mark Vandermeulen ,  Andrew Cervin-Lawry ,  Atin Patel

Inventor： Ivoyl Koutsaroff ,  Mark Vandermeulen ,  Andrew Cervin-Lawry ,  Atin Patel

IPC: H01L29/32 ,  H05K3/10

CPC classification number: H01G4/38 ,  H01G4/33 ,  H01G13/04 ,  H01L27/016 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/38 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).

Abstract translation: 根据本文所述的教导，提供了陶瓷基板上的多层薄膜电容器及其制造方法。 多层薄膜电容器（MLC）可以在至少两个电极层之间包括至少一个高介电常数介电层，电极层由导电薄膜材料形成。 陶瓷基板和薄膜MLC之间可以包括缓冲层。 缓冲层可以具有小于或等于0.08微米（μm）的表面粗糙度（Ra）的光滑表面。

公开(公告)号：US07253502B2

公开(公告)日：2007-08-07

申请号：US10900385

申请日：2004-07-28

Applicant: Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

Inventor： Subahu D. Desai ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich ,  David L. Thomas

IPC: H01L23/58

CPC classification number: G11C11/22 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/16 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/0401

Abstract: A circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The substrate is preferably combined with other dielectric-circuit layered assemblies to form a multilayered substrate on which can be positioned discrete electronic components (e.g., a logic chip) coupled to the internal memory device to work in combination therewith. An electrical assembly capable of using the substrate is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.

Abstract translation: 一种电路化衬底，由至少一层具有导电图案的电介质材料构成。 图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成 设备。 衬底优选地与其它介电电路分层组件组合以形成多层衬底，在多层衬底上，可以将耦合到内部存储器件的分立电子部件（例如，逻辑芯片）放置在其上以与之组合工作。 还提供了能够使用基板的电气组件，以及适于使用一个或多个这样的电气组件作为其一部分的信息处理系统。