公开(公告)号：US07040013B1

公开(公告)日：2006-05-09

申请号：US10390368

申请日：2003-03-17

Applicant: Daniel A. Jochym ,  Christian E. Shenberger ,  Robert Fix

Inventor： Daniel A. Jochym ,  Christian E. Shenberger ,  Robert Fix

IPC: H05K3/02

CPC classification number: H05K1/0216 ,  H05K1/112 ,  H05K1/115 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/09609 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49718

Abstract: A method, system, and product for routing nets along a printed circuit board through an obstacle field and a circuit board having traces produced in accordance with the routed nets is disclosed. The nets are routed by identifying a general path for each of a pair of nets between adjacent rows of obstacles within an obstacle field, selectively lengthening at least one of the nets by shifting at least one portion of the net toward a position between adjacent pads in one of the rows, thereby increasing the length of the net, and selectively increasing the mean spacing between the pair of nets by shifting at least one portion of at least one net of the pair away from the other net of the pair toward a position between adjacent pads in one of the rows, thereby reducing cross-talk between the nets.

Abstract translation: 公开了一种用于通过障碍物场沿着印刷电路板路由网络的方法，系统和产品，以及具有根据所传送的网络产生的迹线的电路板。 通过识别障碍物区域内的相邻障碍物排之间的一对网络中的每一个网络的通用路径来路由网络，通过将网络的至少一部分移向相邻焊盘之间的位置来选择性地延长网络中的至少一个网络 从而增加网的长度，并且通过将对中的至少一个网的至少一个部分从另一个网络的至少一个部分移动到另一个网络之间的位置来选择性地增加该对网之间的平均间隔 在一行中的相邻焊盘，从而减少网之间的串扰。

公开(公告)号：US07005955B2

公开(公告)日：2006-02-28

申请号：US10421066

申请日：2003-04-23

Applicant: Richard A. Schumacher

Inventor： Richard A. Schumacher

IPC: H01F5/00 ,  H01F27/24

CPC classification number: H05K1/165 ,  H01F17/0013 ,  H01F17/0033 ,  H01F17/04 ,  H01F27/2804 ,  H01F41/046 ,  H05K3/181 ,  H05K3/244 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/086 ,  H05K2201/09609

Abstract: One embodiment of the invention is an inductor that is formed on a printed circuit board comprising a core of ferromagnetic material that is formed on a layer of the printed circuit board, and a winding that surrounds a portion of the core and is formed from a plurality of vias in the printed circuit board.

Abstract translation: 本发明的一个实施例是形成在印刷电路板上的电感器，该印刷电路板包括形成在印刷电路板的层上的铁磁材料芯，以及围绕芯的一部分并由多个芯体形成的绕组 的印刷电路板中的通孔。

公开(公告)号：US20050201065A1

公开(公告)日：2005-09-15

申请号：US11056831

申请日：2005-02-11

Applicant: Kent Regnier ,  David Brunker ,  Martin Ogbuokiri

Inventor： Kent Regnier ,  David Brunker ,  Martin Ogbuokiri

IPC: H01L23/64 ,  H01L23/66 ,  H01R12/16 ,  H01R13/658 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/0245 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board design is disclosed that is useful in high-speed differential signal applications uses either a via arrangement or a circuit trace exit structure. In the via arrangement, sets of differential signal pair vias and an associated ground are arranged adjacent to each other in a repeating pattern. The differential signal vias of each pair are spaced closer to their associated ground via than the spacing between the adjacent differential signal pair associated ground so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias. The circuit trace exit structure involves the exit portions of the circuit traces of the differential signal vias to follow a path where they meet with and join to the transmission lines portions of the traces.

Abstract translation: 公开了一种在高速差分信号应用中使用电路板设计或电路走线出口结构的电路板设计。 在通孔布置中，差分信号对通孔和相关接地的组以重复图案彼此相邻布置。 每对的差分信号通孔比相邻的差分信号对相关联的接地之间的间隔更靠近其相关联的接地间隔，使得差分信号通孔表现出对它们相关的接地通孔的电耦合的偏好。 电路走线出口结构涉及差分信号通路的电路迹线的出口部分，以跟随它们与路线的传输线部分相遇并连接到路径的路径。

公开(公告)号：US20050195051A1

公开(公告)日：2005-09-08

申请号：US10796398

申请日：2004-03-08

Applicant: William McKinzie

Inventor： William McKinzie

IPC: H01P1/20 ,  H01P7/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/16

CPC classification number: H01P1/20 ,  H01P1/2005 ,  H05K1/0216 ,  H05K1/0236 ,  H05K1/0239 ,  H05K1/115 ,  H05K1/162 ,  H05K2201/09609 ,  H05K2201/09672

Abstract: Systems and methods are taught for blocking the propagation of electromagnetic waves in parallel-plate waveguide (PPW) structures. Periodic arrays of resonant vias are used to create broadband high frequency stop bands in the PPW, while permitting DC and low frequency waves to propagate. Some embodiments of resonant via arrays are mechanically balanced, which promotes improved manufacturability. Important applications include electromagnetic noise reduction in layered electronic devices such as circuit boards, ceramic modules, and semiconductor chips.

Abstract translation: 教导系统和方法阻止平行板波导（PPW）结构中电磁波的传播。 谐振通孔的周期阵列用于在PPW中产生宽带高频阻带，同时允许DC和低频波传播。 谐振通孔阵列的一些实施例是机械平衡的，这促进了改进的可制造性。 重要的应用包括诸如电路板，陶瓷模块和半导体芯片的分层电子设备中的电磁噪声降低。

公开(公告)号：US20050104678A1

公开(公告)日：2005-05-19

申请号：US10937251

申请日：2004-09-10

Applicant: Shahrooz Shahparnia ,  Omar Ramahi

Inventor： Shahrooz Shahparnia ,  Omar Ramahi

IPC: H04B3/28 ,  H05K1/00 ,  H05K1/02

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09781

Abstract: Electromagnetic Bandgap (EBG) structures are embedded between adjacent power planes in a multi-layer PCB to decrease the emanation of Electromagnetic radiation induced by power buses, signal layers, as well as to suppress the switching noise. EBG stages with different stop bands are cascaded to create rejection over a wider frequency region. The cascading can be performed in series, or may be formed in a variety of arrangements such as a checkerboard design or concentric ribbons positioned along the perimeter of the PCB. Each EBG stage is composed of conductive patches and via posts extending from each patch, which are positioned at a predetermined distance from each other. By surrounding the source of the noise with EBG stages, a sufficient suppression of electromagnetic noise over specific frequency bands of interest is achieved.

Abstract translation: 电磁带隙（EBG）结构嵌入在多层PCB中的相邻电源层之间，以减少由电力总线，信号层引起的电磁辐射的发射，并抑制开关噪声。 具有不同阻带的EBG级联级联以在更宽的频率区域上产生抑制。 级联可以串联执行，或者可以以各种布置形成，例如沿着PCB的周边定位的棋盘设计或同心带。 每个EBG阶段由导电贴片和从每个贴片延伸的通孔构成，每个贴片彼此以预定距离定位。 通过用EBG级围绕噪声源，实现了对感兴趣的特定频带的电磁噪声的充分抑制。

公开(公告)号：US20050093133A1

公开(公告)日：2005-05-05

申请号：US10701311

申请日：2003-11-04

Applicant: Kazushige Kawasaki ,  Irving Memis

Inventor： Kazushige Kawasaki ,  Irving Memis

IPC: H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H01L29/40

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/029 ,  H05K2201/09609 ,  H05K2201/09627

Abstract: The density of plated thru holes in a glass fiber based chip carrier is increased by off-setting holes to positions in which fibers from adjacent holes will not connect. Elongated strip zones or regions having a width approximately the diameter of the holes and running along orthogonal columns and rows of holes, parallel to the direction of fibers, define regions of fibers that can possibly cause shorting between holes. Rotating a conventional X-Y grid pattern of equidistant holes so as to position, for example, alternate holes in one direction between the elongated strip zones running in the opposite direction significantly increases the distance between holes along the elongated strip zones running in each direction. The holes are positioned between elongated strip zones with sufficient clearance to compensate for variations in the linear path of fibers.

Abstract translation: 基于玻璃纤维的芯片载体中的电镀通孔的密度通过偏移孔增加到相邻孔的纤维将不连接的位置。 宽度大约为孔的宽度的区域或区域平行于纤维方向的正交列和孔排沿着孔的直径延伸，限定了可能导致孔之间短路的纤维区域。 旋转等距孔的常规X-Y网格图案，以便例如在沿相反方向运行的细长条带之间的一个方向上的交替孔定位显着地增加沿着沿每个方向运行的细长条带的孔之间的距离。 孔位于具有足够间隙的细长带区之间以补偿纤维线性路径的变化。

公开(公告)号：US20040265482A1

公开(公告)日：2004-12-30

申请号：US10851091

申请日：2004-05-24

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yasuyoshi Horikawa ,  Akio Rokugawa ,  Takahiro Iijima

IPC: B05D005/12

CPC classification number: H01L21/486 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K3/4046 ,  H05K3/445 ,  H05K3/4602 ,  H05K3/4608 ,  H05K2201/0195 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/10378 ,  H05K2201/10416 ,  H05K2203/025 ,  H01L2224/0401

Abstract: The present invention includes the steps of preparing a core substrate having a through hole therein, arranging the conductive parts in the through hole in a state that a top end side of the conductive parts forms a projected portion projected from the core substrate, by inserting a conductive parts having a length, which is longer than a thickness of the core substrate, into the through hole of the core substrate, forming an insulating film on the core substrate to coat the projected portion of the conductive parts, and planarizing the insulating film by grinding the insulating film.

Abstract translation: 本发明包括以下步骤：制备在其中具有通孔的芯基板，其中导电部分设置在通孔中，导电部分的顶端侧形成从芯基板突出的突出部分的状态， 具有比核心基板的厚度长的长度的导电部件插入到芯基板的通孔中，在芯基板上形成绝缘膜以涂覆导电部件的突出部分，并且通过 研磨绝缘膜。

公开(公告)号：US20040188135A1

公开(公告)日：2004-09-30

申请号：US10403148

申请日：2003-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： William Louis Brodsky ,  Mark Kenneth Hoffmeyer ,  James R. Stack

IPC: H05K007/06 ,  H05K003/46

CPC classification number: H05K1/0271 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/112 ,  H05K2201/0191 ,  H05K2201/093 ,  H05K2201/09609 ,  H05K2201/09681 ,  H05K2201/09718 ,  H05K2201/10719 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method and structure are provided for implementing enhanced interconnection performance of an electrical connector, such as a land grid array (LGA) module, and a printed wiring board. A multi-layer printed wiring board includes a plurality of predefined ground and power layers. At least one of the predefined ground and power layers includes a thickness variation minimizing structure for minimizing thickness variation. The thickness variation minimizing structure includes a perforated pattern within a selected area of the at least one of the predefined ground and power layers. The selected area is proximate to predefined module sites, such as land grid array (LGA) module sites, in the ground and power layers. The selected area can include regions surrounding each predefined module site, and also can include a region within the module site.

Abstract translation: 提供了一种用于实现电连接器（例如，平面栅格阵列（LGA）模块）和印刷电路板的增强的互连性能的方法和结构。 多层印刷线路板包括多个预定义的接地层和功率层。 预定义的接地层和功率层中的至少一个包括用于最小化厚度变化的厚度变化最小化结构。 厚度变化最小化结构包括在预定义的接地层和功率层中的至少一个的选定区域内的穿孔图案。 所选择的区域靠近预定义的模块站点，例如地面和电力层中的陆地网格阵列（LGA）模块站点。 所选择的区域可以包括围绕每个预定义模块站点的区域，并且还可以包括模块站点内的区域。

公开(公告)号：US06797616B2

公开(公告)日：2004-09-28

申请号：US10225907

申请日：2002-08-21

Applicant: Larry D. Kinsman

Inventor： Larry D. Kinsman

IPC: H01L2144

CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09945 ,  H01L2924/00

Abstract: The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board and extending from one surface of the board to the other. Conductive traces extend along the surface of the circuit board from the conduction elements to the integrated circuits. The conductive traces may be formed from multiple conductive layers.

公开(公告)号：US06721187B2

公开(公告)日：2004-04-13

申请号：US09811101

申请日：2001-03-16

Applicant: Richard Ronald Hall ,  How Tzu Lin ,  Christopher John Majka ,  Norman Corey Seastrand ,  Matthew Francis Seward ,  Ronald Verne Smith

Inventor： Richard Ronald Hall ,  How Tzu Lin ,  Christopher John Majka ,  Norman Corey Seastrand ,  Matthew Francis Seward ,  Ronald Verne Smith

IPC: H05K702

CPC classification number: H05K3/403 ,  H01R12/52 ,  H05K1/0306 ,  H05K1/118 ,  H05K3/3405 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0919 ,  H05K2201/09609 ,  H05K2201/10446 ,  H05K2201/10734

Abstract: A multi-layer electronic structure includes an increased capacity for the attachment of active or passive devices thereto. This is achieved by creating a three-dimensional grid of connection points to electrically couple active or passive surface mounted devices to edge mounted devices. The grid pattern is useful with any laminate including circuit cards, ceramic modules and flexible circuits. The variety of electrical devices that may be connected to the cross-sectional substrate includes, but is not limited to, chips such as semiconductor chips, diodes, resistors, capacitors and printed wiring boards. The structure can be used to more rapidly pass data, such as optical data that is transmitted from a spectroscope through a VCSEL laser and the electronic structure to a computer for diagnostics and analysis. A stepped arrangement of circuitized laminates is described for this purpose.

Abstract translation: 多层电子结构包括用于将主动或无源装置附接到其上的增加的容量。 这通过创建连接点的三维网格来将主动或被动表面安装的装置电耦合到边缘安装的装置来实现。 网格图案对于包括电路卡，陶瓷模块和柔性电路的任何层压板都是有用的。 可以连接到横截面基板的各种电气设备包括但不限于诸如半导体芯片，二极管，电阻器，电容器和印刷线路板的芯片。 该结构可用于更快速地传递数据，例如通过VCSEL激光器从分光镜传输的光学数据，以及用于诊断和分析的电子结构到计算机。 为此目的描述了电路化层压板的阶梯式布置。