公开(公告)号：US09258897B2

公开(公告)日：2016-02-09

申请号：US13484381

申请日：2012-05-31

Applicant: Teruyuki Ishihara ,  Hidetoshi Noguchi ,  Hirofumi Futamura

Inventor： Teruyuki Ishihara ,  Hidetoshi Noguchi ,  Hirofumi Futamura

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H05K3/46

CPC classification number: H05K1/183 ,  H05K3/3452 ,  H05K3/4691 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09127 ,  H05K2201/09136 ,  H05K2201/09854 ,  Y10T29/49128

Abstract: A wiring board has a laminated structure having a recessed portion on a first-surface side of the laminated structure and a solder resist layer on a second-surface side of the laminated structure on the opposite side of the first-surface side. The laminated structure has a first-surface side pad formed in the bottom of the recessed portion and a second-surface side pad formed on the second-surface side of the laminated structure, the solder resist layer has a first opening portion and a second opening portion formed in the solder resist layer, the first opening portion is exposing the second-surface side pad, the second opening portion is formed on a back face of the recessed portion, and the back face of the recessed portion does not include the second-surface side pad.

Abstract translation: 布线基板具有在层叠结构体的第一表面侧具有凹部的层叠结构，在层叠结构体的与第一面侧相反一侧的第二面侧的阻焊层。 该叠层结构具有形成在该凹部的底部的第一表面侧焊盘和形成在层叠结构的第二表面侧的第二表面侧焊盘，该阻焊层具有第一开口部和第二开口 所述第一开口部露出所述第二表面侧焊盘，所述第二开口部形成在所述凹部的背面，所述凹部的背面不包括所述第二表面侧焊盘， 表面侧垫

公开(公告)号：US20150382469A1

公开(公告)日：2015-12-31

申请号：US14492716

申请日：2014-09-22

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Chu-Chin HU ,  Shih-Ping HSU ,  E-Tung CHOU

IPC: H05K1/18 ,  H05K3/40 ,  H05K3/28 ,  H05K1/14 ,  H05K3/34

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/00 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/115 ,  H05K1/187 ,  H05K1/188 ,  H05K3/0014 ,  H05K3/0017 ,  H05K3/007 ,  H05K3/16 ,  H05K3/181 ,  H05K3/284 ,  H05K3/421 ,  H05K2201/0162 ,  H05K2201/0209 ,  H05K2201/09118 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/09636 ,  H05K2201/09854 ,  H05K2203/025 ,  H05K2203/0369 ,  H05K2203/0723 ,  H05K2203/0733 ,  H05K2203/1316 ,  H05K2203/1461 ,  H05K2203/1469 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A package apparatus comprises a first wiring layer, a first conductive pillar layer, a first molding compound layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface that are arranged opposite to each other. The first conductive pillar layer is disposed on the second surface of the first wiring layer, whereas the first conductive pillar layer is a non-circular conductive pillar layer. The first molding compound layer is disposed within a specific portion of the first wiring layer and the first conductive pillar layer. The second wiring layer is disposed on the first molding compound layer and one end of the first conductive pillar layer. The protection layer is disposed on the first molding compound layer and the second wiring layer.

Abstract translation: 包装装置包括第一布线层，第一导电柱层，第一模塑料层，第二布线层和保护层。 第一布线层具有彼此相对布置的第一表面和第二表面。 第一导电柱层设置在第一布线层的第二表面上，而第一导电柱层是非圆形导电柱层。 第一模塑料层设置在第一布线层和第一导电柱层的特定部分内。 第二布线层设置在第一模塑料层和第一导电柱层的一端。 保护层设置在第一模塑料层和第二布线层上。

公开(公告)号：US20150366066A1

公开(公告)日：2015-12-17

申请号：US14528804

申请日：2014-10-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae-Seong KIM ,  Yeon-Seop YU ,  Bok-Hee LEE

IPC: H05K1/18 ,  H05K3/00 ,  H05K3/30

CPC classification number: H05K1/185 ,  H05K1/0271 ,  H05K2201/09072 ,  H05K2201/09827 ,  H05K2201/09854 ,  Y10T29/49131

Abstract: An electronic device embedded substrate and a method of manufacturing the same are disclosed. The electronic device embedded substrate in accordance with an aspect of the present invention includes: an electronic device; and a core substrate having a cavity, in which the electronic device is embedded and of which a width of at least a portion is smaller than widths of other portions thereof.

Abstract translation: 公开了一种电子器件嵌入式基板及其制造方法。 根据本发明的一个方面的电子设备嵌入式基板包括：电子设备; 以及具有空腔的芯基板，其中嵌入有电子器件，其中至少一部分的宽度小于其它部分的宽度。

公开(公告)号：US20150334842A1

公开(公告)日：2015-11-19

申请号：US14713064

申请日：2015-05-15

Applicant: IBIDEN CO., LTD.

Inventor： Toyotaka SHIMABE ,  Ryuichiro Tominaga

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/183 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0145 ,  H05K2201/09854 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10219 ,  H05K2201/10636 ,  H05K2203/1469 ,  Y02P70/611 ,  H01L2924/00

Abstract: A printed wiring board includes a core substrate having a cavity, multiple electronic components accommodated in the cavity, and a build-up layer formed on the substrate and including an insulating interlayer such that the interlayer is covering the cavity. The components include a first component, second component and third component, the core substrate has a first projection structure partitioning the first and second components in the cavity and a second projection structure partitioning the second and third components in the cavity, and the cavity and the first and second structures are formed in the substrate such that T1

Abstract translation: 印刷电路板包括具有空腔的芯基板，容纳在空腔中的多个电子元件，以及形成在基板上并包括绝缘夹层的堆积层，使得中间层覆盖空腔。 所述部件包括第一部件，第二部件和第三部件，所述芯基板具有分隔所述空腔中的所述第一和第二部件的第一突起结构以及将所述腔体中的第二和第三部件分隔开的第二突起结构， 在基板上形成第一和第二结构，使得T1

公开(公告)号：US09049799B2

公开(公告)日：2015-06-02

申请号：US14021189

申请日：2013-09-09

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Daisuke Takizawa

IPC: H05K1/18 ,  H05K3/46 ,  H01L23/50 ,  H01L23/498

CPC classification number: H05K1/184 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/1531 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09854 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A wiring substrate is provided with a core substrate including a first main surface, a second main surface, and a through hole. An electronic component including a resin cover is arranged in the through hole. A projection projects from an inner wall of the through hole toward the resin cover of the electronic component. An insulator is filled between the inner wall of the through hole and the electronic component. A first insulation layer covers the electronic component and the first main surface. A second insulation layer covers the electronic component and the second main surface. The resin cover of the electronic component includes an engagement groove formed by the projection and extending along a direction in which the electronic component is fitted into the through hole.

Abstract translation: 布线基板设置有包括第一主表面，第二主表面和通孔的芯基板。 包括树脂盖的电子部件布置在通孔中。 突起从通孔的内壁朝向电子部件的树脂盖突出。 绝缘体填充在通孔的内壁和电子部件之间。 第一绝缘层覆盖电子部件和第一主表面。 第二绝缘层覆盖电子部件和第二主表面。 电子部件的树脂盖包括由突起形成并且沿着电子部件嵌入通孔的方向延伸的接合槽。

公开(公告)号：US20150136467A1

公开(公告)日：2015-05-21

申请号：US14408039

申请日：2013-03-13

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： James Rathburn

IPC: H01R12/77 ,  H01R12/82 ,  H01R12/79

CPC classification number: H01R23/6813 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01R12/73 ,  H01R12/82 ,  H01R13/2457 ,  H01R13/2485 ,  H01R31/06 ,  H05K1/092 ,  H05K1/111 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/1291 ,  H05K3/326 ,  H05K3/363 ,  H05K3/365 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4092 ,  H05K3/425 ,  H05K3/4694 ,  H05K7/1076 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09381 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/2072 ,  H05K2201/209 ,  H05K2203/041 ,  H05K2203/1476 ,  Y10T29/49165 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.

Abstract translation: 一种在电路组件上制成集成端子阵列的方法。 该方法包括以下步骤：在第一电路构件的第一表面上沉积至少第一液体电介质层，成像为包括与集成端子阵列相对应的多个第一凹部。 处理第一凹槽的选定表面以接受无电导电电镀沉积。 对所述第一凹槽的所选择的表面施加无电镀以产生电耦合到所述第一电路层并且大致垂直于所述第一电路层延伸的多个第一导电结构。 使用导电材料将电镀施加到基本上第一凹部的无电镀。 重复沉积，加工，无电镀和电镀的步骤以形成所需形状的整体端子。 去除电介质层以露出端子。

公开(公告)号：US20150131231A1

公开(公告)日：2015-05-14

申请号：US14267456

申请日：2014-05-01

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Do Jae YOO ,  Jong In Ryu ,  Eun Jung Jo ,  Jae Hyun Lim ,  Kyu Hwan Oh

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/30 ,  H05K1/18

CPC classification number: H05K3/4007 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/19105 ,  H05K1/0209 ,  H05K1/11 ,  H05K1/113 ,  H05K1/185 ,  H05K3/284 ,  H05K2201/09563 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/1316 ,  Y10T29/49146 ,  H01L2924/00014

Abstract: There are provided an electronic component module allowing for a circuit wiring to be disposed outside of a molded part by a plating process, and a manufacturing method thereof, the electronic component module including a substrate; at least one electronic component mounted on the substrate; a molded part sealing the electronic component; a plurality of conductive connectors having one ends bonded to the substrate or one surface of the electronic component and formed in the molded part to penetrate through the molded part; and at least one plane pattern formed on an outer surface of the molded part and electrically connected to at least one of the conductive connectors.

Abstract translation: 提供一种电子部件模块，其允许电路布线通过电镀工艺设置在模制部件的外部，及其制造方法，所述电子部件模块包括基板; 安装在所述基板上的至少一个电子部件; 密封电子部件的模制部件; 多个导电连接器，其一端接合到所述基板或所述电子部件的一个表面，并且形成在所述模制部件中以穿透所述模制部件; 以及形成在所述模制部件的外表面上并电连接到所述导电连接器中的至少一个的至少一个平面图案。

公开(公告)号：US08999537B2

公开(公告)日：2015-04-07

申请号：US13326169

申请日：2011-12-14

Applicant: Eunyoung Kim

Inventor： Eunyoung Kim

IPC: H01M14/00 ,  H05K1/11 ,  H01M10/42 ,  H01M2/10 ,  H05K3/34 ,  H05K3/30

CPC classification number: H01M10/425 ,  H01M2/1066 ,  H05K3/306 ,  H05K3/3447 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/10037

Abstract: A battery pack configured to prevent excess solder material from flowing down onto a protective circuit module (PCM) is disclosed. According to some aspects, the battery pack includes at least one battery cell, a protective circuit module (PCM) electrically connected to the battery cell, and a conductive tab configured to electrically connect the battery cell to the PCM. A tapered through hole is formed in the PCM so that the conductive tab is inserted into and fixed to the through hole.

Abstract translation: 公开了一种电池组，其被配置为防止多余的焊料材料向下流到保护电路模块（PCM）上。 根据一些方面，电池组包括至少一个电池单元，电连接到电池单元的保护电路模块（PCM）和被配置为将电池单元电连接到PCM的导电接头。 在PCM中形成锥形通孔，使得导电片插入并固定到通孔。

公开(公告)号：US20150092356A1

公开(公告)日：2015-04-02

申请号：US14504842

申请日：2014-10-02

Applicant: IBIDEN CO., LTD.

Inventor： Kazuhiro YOSHIKAWA ,  Takashi Kariya

IPC: H05K1/03 ,  H05K3/04 ,  H05K3/18 ,  H05K3/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/113 ,  H01L25/00 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/144 ,  H05K1/183 ,  H05K3/244 ,  H05K3/282 ,  H05K3/3473 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/096 ,  H05K2201/09854 ,  H05K2203/0392 ,  H05K2203/0577 ,  H05K2203/0723 ,  H05K2203/1383 ,  Y10T29/49156

Abstract: A method for manufacturing a printed wiring board includes forming a removable layer over first pads in central portion of an interlayer insulation layer to mount IC chip, forming on the interlayer and removable layers a resin insulation layer having openings exposing second pads in peripheral portion of the interlayer layer to connect second substrate, forming a seed layer on the resin layer, in the openings and on the second pads, forming on the seed layer a plating resist having resist openings exposing the openings of the resin layer with diameters greater than the openings, filling the resist openings with electrolytic plating such that metal posts are formed in the resist openings, removing the resist, removing the seed layer exposed on the resin layer, and removing the removable layer and the resin layer on the removable layer such that cavity exposing the first pads is formed in the resin layer.

Abstract translation: 一种制造印刷电路板的方法，包括在层间绝缘层的中心部分的第一焊盘上形成可移除层以安装IC芯片，在中间层和可去除层上形成具有露出第二焊盘的开口的树脂绝缘层， 层间层，用于连接第二基板，在树脂层上，在开口和第二焊盘上形成种子层，在种子层上形成具有抗蚀剂开口的电镀抗蚀剂，该抗蚀剂开口露出具有大于开口的直径的树脂层的开口， 通过电解电镀填充抗蚀剂开口，使得在抗蚀剂开口中形成金属柱，去除抗蚀剂，除去暴露在树脂层上的种子层，以及去除可去除层上的可去除层和树脂层， 在树脂层中形成第一焊盘。

公开(公告)号：US08952262B2

公开(公告)日：2015-02-10

申请号：US13599326

申请日：2012-08-30

Applicant: Daisuke Yamashita ,  Kazunaga Higo ,  Tetsuji Tsukada

Inventor： Daisuke Yamashita ,  Kazunaga Higo ,  Tetsuji Tsukada

IPC: H05K1/16 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H01L23/64 ,  H01L23/498 ,  H05K3/46 ,  H05K1/02 ,  H01L23/50

CPC classification number: H05K1/185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2203/1469 ,  Y02P70/611 ,  Y10T29/49139

Abstract: A component-incorporated wiring substrate is provided. Some embodiments include a plate-like component incorporated in a core substrate and a build-up layer having an insulation layer and a conductor layer disposed in alternating layers. The component has terminal electrodes formed at its opposite ends having a side surface and a main surface. An insulation layer disposed on the main surface of the component has via conductors formed therein which are connected to the side surfaces and the main surfaces of the respective terminal electrodes. The via conductors are tapered, such that their via diameter decreases in a direction toward the terminal electrode, and their via diameter at a position where they connect to the main surface is greater than a length of the main surface. Accordingly, the area of connection between the via conductors and the corresponding terminal electrodes is increased, improving connection reliability through enhancement of tolerance for positional deviation.

Abstract translation: 提供了一种构成部件的布线基板。 一些实施例包括结合在芯基板中的板状部件和具有设置在交替层中的绝缘层和导体层的堆积层。 该部件具有在其相对端形成的端子电极，其侧表面和主表面。 设置在部件的主表面上的绝缘层具有形成在其中的通孔导体，其连接到各个端子电极的侧表面和主表面。 通孔导体是锥形的，使得它们的通孔直径在朝向端子电极的方向上减小，并且它们在它们连接到主表面的位置处的通孔直径大于主表面的长度。 因此，通孔导体与对应的端子电极之间的连接面积增加，通过增加位置偏差的公差来提高连接的可靠性。