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    Fabrication method of semiconductor piece
    153.
    发明授权
    Fabrication method of semiconductor piece 有权
    半导体片的制作方法

    公开(公告)号：US09589812B2

    公开(公告)日：2017-03-07

    申请号：US14884168

    申请日：2015-10-15

    Applicant: FUJI XEROX CO., LTD.

    Inventor： Mutsuya Takahashi ,  Shuichi Yamada ,  Michiaki Murata

    IPC: H01L21/3065 ,  H01L21/304 ,  H01L21/02 ,  B81C1/00 ,  H01L21/78 ,  H01L21/683

    CPC classification number: H01L21/3065 ,  B81C1/00531 ,  B81C1/00619 ,  B81C2201/0132 ,  H01L21/02225 ,  H01L21/3043 ,  H01L21/30621 ,  H01L21/6836 ,  H01L21/78 ,  H01L33/0095 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01S5/0201 ,  H01S5/0202

    Abstract: A fabrication method of a semiconductor piece includes forming a groove that has a first groove portion, and a second groove portion which is a groove portion formed to communicate with a lower part of the first groove portion and extends toward a lower part at a steeper angle than an angle of the first groove portion, has a shape without an angle portion between the first groove portion and the second groove portion, is positioned on the front side, and is formed by dry etching; affixing a retention member including an adhesive layer to the surface in which the groove on the front side is formed; thinning the substrate from the back side of the substrate in a state in which the retention member is affixed; and removing the retention member from the surface after the thinning.

    Abstract translation: 半导体器件的制造方法包括形成具有第一槽部的槽和形成为与第一槽部的下部连通并且以更陡的角度向下方延伸的槽部的第二槽部 与第一槽部的角度相比，具有在第一槽部和第二槽部之间没有角部的形状位于前侧，通过干蚀刻形成; 将包括粘合剂层的保持构件固定到其上形成有所述凹槽的表面; 在保持部件固定的状态下，从基板的背面使基板变薄; 并且在变薄之后从表面移除保持构件。

    Micro-structured atomic source system
    154.
    发明授权
    Micro-structured atomic source system 有权
    微结构原子源系统

    公开(公告)号：US09585237B2

    公开(公告)日：2017-02-28

    申请号：US14682810

    申请日：2015-04-09

    Applicant: Honeywell International Inc.

    Inventor： James Goeders ,  Matthew S. Marcus ,  Thomas Ohnstein ,  Terry Dean Stark

    IPC: H01S1/00 ,  H05H3/02

    CPC classification number: H05H3/02 ,  B81B7/02 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C2201/0132 ,  B81C2201/0133

    Abstract: A micro-structured atomic source system is described herein. One system includes a silicon substrate, a dielectric diaphragm, wherein the dielectric diaphragm includes a heater configured to heat an atomic source substance, an intermediary material comprising a chamber configured to receive the atomic source substance, and a guide material configured to direct a flux of atoms from the atomic source substance.

    Abstract translation: 本文描述了微结构的原子源系统。 一个系统包括硅衬底，介质隔膜，其中介质隔膜包括构造成加热原子源物质的加热器，包括被配置为接纳原子源物质的室的中间材料，以及引导材料， 原子来源物质的原子。

    Method of bonding two substrates and device manufactured thereby
    155.
    发明授权
    Method of bonding two substrates and device manufactured thereby 有权
    接合两个基板的方法和由此制造的装置

    公开(公告)号：US09573804B2

    公开(公告)日：2017-02-21

    申请号：US14361683

    申请日：2012-12-21

    Applicant: Micronit Microfluidics B.V.

    Inventor： Ronny Van 'T Oever ,  Marko Theodoor Blom ,  Jeroen Haneveld ,  Johannes Oonk ,  Marinus Bernardus Olde Riekerink ,  Peter Tijssen ,  Hendrik Jan Hildebrand Tigelaar ,  Jean-Noël Fehr ,  Jean-Christophe Roulet ,  Amitava Gupta

    IPC: B81C1/00 ,  H01L23/10 ,  H01L21/50 ,  B81C3/00 ,  C23F1/02

    CPC classification number: B81C1/00269 ,  B81B2201/058 ,  B81C3/001 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/019 ,  C23F1/02 ,  H01L21/50 ,  H01L23/10 ,  H01L2924/0002 ,  Y10T428/239 ,  H01L2924/00

    Abstract: The invention relates to method for bonding at least two substrates, for example made from glass, silicon, ceramic, aluminum, or boron, by using an intermediate thin film metal layer for providing the bonding, said method comprising the following steps of: a) providing said two substrates; b) depositing said thin film metal layer on at least a part of a surface of a first substrate of the two substrates; c) bringing a surface of the second substrate into contact with said thin film metal layer on said surface of the first substrate such that a bonding between the second substrate and the thin film metal layer on the first substrate is provided; and d) at least locally strengthening the bonding between the second substrate and the thin film metal layer on the first substrate. The invention also relates to a device comprising two substrates, for example made from glass, silicon, ceramic, aluminum, or boron, and an intermediate thin film metal layer.

    Abstract translation: 本发明涉及通过使用用于提供接合的中间薄膜金属层将至少两个基板（例如由玻璃，硅，陶瓷，铝或硼制成）接合的方法，所述方法包括以下步骤：a） 提供所述两个基板; b）将所述薄膜金属层沉积在所述两个基板的第一基板的表面的至少一部分上; c）使所述第二基板的表面与所述第一基板的所述表面上的所述薄膜金属层接触，从而提供所述第二基板和所述第一基板上的所述薄膜金属层之间的接合; 以及d）至少局部加强第一基板上的第二基板和薄膜金属层之间的接合。 本发明还涉及包括例如由玻璃，硅，陶瓷，铝或硼制成的两个基底和中间薄膜金属层的器件。

    MONOLITHIC CMOS-MEMS MICROPHONES AND METHOD OF MANUFACTURING
    156.
    发明申请
    MONOLITHIC CMOS-MEMS MICROPHONES AND METHOD OF MANUFACTURING 有权
    单片CMOS-MEMS微波阵列及其制造方法

    公开(公告)号：US20170044008A1

    公开(公告)日：2017-02-16

    申请号：US15339760

    申请日：2016-10-31

    Applicant: Robert Bosch GmbH

    Inventor： John Zinn ,  Brett Diamond ,  Jochen Hoffmann

    IPC: B81C1/00 ,  H04R31/00

    CPC classification number: B81C1/00246 ,  B81B2201/0257 ,  B81C2201/0132 ,  H04R31/00 ,  H04R31/003 ,  H04R2201/003

    Abstract: Systems and methods are disclosed for manufacturing a CMOS-MEMS device. A partial protective layer is deposited on a top surface of a layered to cover a logic region. A first partial etch is performed from the bottom side of the layered structure to form a first gap below a MEMS membrane within a MEMS region of the layered structure. A second partial etch is performed from the top side of the layered structure to remove a portion of a sacrificial layer between the MEMS membrane and a MEMS backplate within the MEMS region. The second partial etch releases the MEMS membrane so that it can move in response to pressures. The deposited partial protective layer prevents the second partial etch from etching a portion of the sacrificial layer positioned within the logic region of the layered structure and also prevents the second partial etch from damaging the CMOS logic component.

    Abstract translation: 公开了用于制造CMOS-MEMS器件的系统和方法。 部分保护层沉积在层叠的顶表面上以覆盖逻辑区域。 从分层结构的底侧执行第一部分蚀刻，以在分层结构的MEMS区域内的MEMS膜下方形成第一间隙。 从分层结构的顶侧执行第二部分蚀刻以去除MEMS区域内的MEMS膜和MEMS背板之间的牺牲层的一部分。 第二部分蚀刻释放MEMS膜，使得其可以响应于压力移动。 沉积的部分保护层防止第二部分蚀刻蚀刻位于层状结构的逻辑区域内的牺牲层的一部分，并且还防止第二部分蚀刻损坏CMOS逻辑部件。

    RELEASE CHEMICAL PROTECTION FOR INTEGRATED COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) AND MICRO-ELECTRO-MECHANICAL (MEMS) DEVICES
    158.
    发明申请
    RELEASE CHEMICAL PROTECTION FOR INTEGRATED COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) AND MICRO-ELECTRO-MECHANICAL (MEMS) DEVICES 审中-公开
    用于集成的补充金属氧化物半导体（CMOS）和微机电（MEMS）器件的化学保护

    公开(公告)号：US20170015547A1

    公开(公告)日：2017-01-19

    申请号：US15281589

    申请日：2016-09-30

    Applicant: INVENSENSE, INC.

    Inventor： Michael J. Daneman ,  Fariborz Assaderaghi

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00246 ,  B81B7/0025 ,  B81B7/007 ,  B81B2207/015 ,  B81C1/00531 ,  B81C1/00539 ,  B81C1/00801 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/053 ,  B81C2203/0735

    Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

    Abstract translation: 提供了保护CMOS层免于暴露于释放化学品的系统和方法。 释放化学品用于释放与CMOS晶片集成的微机电（MEMS）器件。 在互补金属氧化物半导体（CMOS）晶片中产生的钝化开口的侧壁暴露了CMOS释放化学品接触时可能损坏的CMOS晶片的电介质层。 在一个方面，为了保护CMOS晶片并防止电介质层的暴露，钝化开口的侧壁可以被抵抗释放化学品的金属阻挡层覆盖。 另外或可选地，可以在CMOS晶片的表面上沉积绝缘阻挡层，以保护钝化层免于暴露于释放化学品。

    METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL
    159.
    发明申请
    METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL 有权
    使用外加材料增加MEMS外壳压力的方法

    公开(公告)号：US20170001861A1

    公开(公告)日：2017-01-05

    申请号：US15265668

    申请日：2016-09-14

    Applicant: InvenSense, Inc.

    Inventor： Cerina ZHANG ,  Martin LIM ,  Jongwoo SHIN ,  Joseph SEEGER

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/0023 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00269 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.

    Abstract translation: 半导体制造工艺包括提供第一衬底，其具有设置在图案化顶层金属层上方的第一钝化层，并且还具有设置在第一钝化层上的第二钝化层; 第二钝化层具有顶表面。 所述方法还包括在第二钝化层的第一部分中形成开口，并且开口暴露第一钝化层的表面的一部分。 所述方法还包括图案化第二钝化层和第一钝化层以暴露图案化顶层金属层的部分并将第二基板和第一基板彼此接合。 接合发生在至少第一钝化层的暴露部分经历脱气的温度范围内。

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