公开(公告)号：US5590465A

公开(公告)日：1997-01-07

申请号：US616954

申请日：1996-03-15

Applicant: Kouichi Santo

Inventor： Kouichi Santo

IPC: H05K1/11 ,  H05K1/00 ,  H05K1/09 ,  H05K3/24 ,  H05K3/28 ,  H05K3/40 ,  H01R43/00

CPC classification number: H05K1/118 ,  H05K1/0393 ,  H05K1/095 ,  H05K2201/0347 ,  H05K2201/09172 ,  H05K3/246 ,  H05K3/281 ,  H05K3/403 ,  Y10T29/49155 ,  Y10T29/49222

Abstract: A conductive metal wiring pattern 1 is printed and wired on a flexible insulation film 2, and has connection terminals 1a whose surfaces are treated into a solderable state by plating or the like. An overriding flexible insulation film 3 is formed such that it covers a portion excluding the connection terminals 1a. The connection terminals 1a are easily formed by printing, bonding and cutting out portions of the insulation film 2 between the connection terminals by a press to separate the connection terminal.

Abstract translation: 将导电金属布线图案1印刷并布线在柔性绝缘膜2上，并且具有通过电镀等将表面处理成可焊接状态的连接端子1a。 形成覆盖柔性绝缘膜3，使得其覆盖除了连接端子1a之外的部分。 连接端子1a通过按压来在绝缘膜2的连接端子的部分之间进行印刷，接合和切割而容易地形成，以分离连接端子。

公开(公告)号：US5571593A

公开(公告)日：1996-11-05

申请号：US467558

申请日：1995-06-06

Applicant: Roy L. Arldt ,  Christina M. Boyko ,  Burtran J. Cayson ,  Richard M. Kozlowski ,  Joseph D. Kulesza ,  John M. Lauffer ,  Philip C. Liu ,  Voya R. Markovich ,  Issa S. Mahmoud ,  James F. Muska ,  Kostas Papathomas ,  Joseph G. Sabia ,  Richard A. Schumacher

Inventor： Roy L. Arldt ,  Christina M. Boyko ,  Burtran J. Cayson ,  Richard M. Kozlowski ,  Joseph D. Kulesza ,  John M. Lauffer ,  Philip C. Liu ,  Voya R. Markovich ,  Issa S. Mahmoud ,  James F. Muska ,  Kostas Papathomas ,  Joseph G. Sabia ,  Richard A. Schumacher

IPC: B32B7/04 ,  C08G59/40 ,  C08G73/00 ,  C08L63/00 ,  C09D163/00 ,  H01B1/20 ,  H01B1/22 ,  H01B1/24 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K3/00 ,  H05K3/40 ,  B32B9/00

CPC classification number: H01B1/24 ,  B32B7/04 ,  H01B1/22 ,  H05K1/095 ,  H05K1/113 ,  H05K1/167 ,  H05K3/4053 ,  H05K3/4069 ,  H01L2224/16235 ,  H05K1/16 ,  H05K2201/0347 ,  H05K2201/09563 ,  H05K2201/10734 ,  H05K2203/0126 ,  H05K2203/0191 ,  H05K2203/0207 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0763 ,  H05K3/0023 ,  H05K3/0047 ,  H05K3/0094 ,  Y10S428/901 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24273 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24826 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/25

Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.

Abstract translation: 本发明允许焊接接头直接制成通孔和通孔，而不会通过用环氧树脂或氰酸盐填充组合物填充电镀通孔，焊料不会被弄脏到通孔或通孔中。 当固化和过度镀覆时，填充组合物为焊接接头提供支撑，并为相互连接提供平坦的可焊接表面。 在某些实施方案中，固化的填充组合物提供另外的导电性的优点。 本发明还涉及用这种填充组合物填充通孔的几种新方法，以及位于通孔和通孔中的电阻器。

公开(公告)号：US5536362A

公开(公告)日：1996-07-16

申请号：US197232

申请日：1994-02-16

Applicant: David G. Love ,  Larry L. Moresco ,  William Tai-Hua Chou ,  David A. Horine ,  Connie M. Wong ,  Solomon I. Beilin

Inventor： David G. Love ,  Larry L. Moresco ,  William Tai-Hua Chou ,  David A. Horine ,  Connie M. Wong ,  Solomon I. Beilin

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/32 ,  H01L23/485 ,  H01L23/498 ,  H05K1/11 ,  H05K3/24 ,  H05K3/34 ,  H05K3/40 ,  H01L21/00 ,  B44C1/22

CPC classification number: H05K3/4007 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L24/02 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/113 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K3/243 ,  H05K3/3436 ,  H05K3/3473

Abstract: Methods of constructing a wire interconnect structure on a substrate are described. The methods broadly comprise the steps of depositing a spacer layer on a surface of the substrate, depositing a mask layer on the spacer layer, and removing a first portion of the mask layer overlying a desired area on the substrate surface to expose the spacer layer underlying the first portion of the mask layer. The methods further comprise the step of etching the structure such that a first portion of the spacer layer overlaying the desired area is removed and such that a portion of the desired area is exposed, and the step of depositing a first conductive material on the exposed portion of the desired area such that a conductive post is formed on the substrate surface and mounted to the desired area. Some of the disclosed methods comprise additional steps for forming an interconnect structure on the opposite surface of the substrate and providing an electrical interconnect means between the two interconnect structures. Additionally, some of the disclosed methods comprise steps for forming fillets around the conductive post at the substrate surface.

Abstract translation: 描述了在基板上构造导线互连结构的方法。 所述方法广泛地包括以下步骤：在衬底的表面上沉积间隔层，在间隔层上沉积掩模层，以及去除覆盖衬底表面上所需区域的掩模层的第一部分，以暴露衬底表面的间隔层 掩模层的第一部分。 所述方法还包括蚀刻该结构的步骤，使得覆盖期望区域的间隔层的第一部分被去除并且使得所需区域的一部分被暴露，以及在暴露部分上沉积第一导电材料的步骤 的所需区域，使得导电柱形成在基板表面上并且安装到期望的区域。 所公开的方法中的一些包括用于在衬底的相对表面上形成互连结构并在两个互连结构之间提供电互连装置的附加步骤。 另外，所公开的方法中的一些包括在基板表面处在导电柱周围形成圆角的步骤。

公开(公告)号：US5507403A

公开(公告)日：1996-04-16

申请号：US375708

申请日：1995-01-20

Applicant: Yukio Sakemura ,  Mitsuru Usui ,  Tetsuya Watanabe

Inventor： Yukio Sakemura ,  Mitsuru Usui ,  Tetsuya Watanabe

IPC: H05K1/03 ,  H05K3/24 ,  H05K3/40 ,  H05K3/46 ,  H01B13/00 ,  B44C1/22 ,  C23F1/00

CPC classification number: H05K3/4605 ,  H05K1/0306 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/096 ,  H05K3/246 ,  H05K3/4061

Abstract: An electronic part is produced by forming two metallic wiring films of different materials on a main substrate, where a first metallic wiring film is formed on the main substrate, a protective film is formed in desired regions on the main substrate and the first metallic wiring film, and a second metallic wiring film is formed on the first metallic wiring film. The thus produced electronic part has an insulating protective film between the first and second metallic wiring films. By the presence of the protective film the surface of the first metallic wiring film is protected from etching, corrosion or deterioration by an agent for patterning the second metallic wiring film.

Abstract translation: 电子部件通过在主基板上形成两种不同材料的金属布线膜来制造，其中在主基板上形成第一金属布线膜，在主基板上的期望区域形成保护膜，并且第一金属布线膜 并且在第一金属布线膜上形成第二金属布线膜。 由此制造的电子部件在第一和第二金属布线膜之间具有绝缘保护膜。 通过保护膜的存在，可以防止第一金属布线膜的表面被用于图案化第二金属布线膜的试剂的蚀刻，腐蚀或劣化。

公开(公告)号：US5468918A

公开(公告)日：1995-11-21

申请号：US167343

申请日：1993-12-16

Applicant: Toshiaki Kanno ,  Makoto Katsumata ,  Hidenori Yamanashi ,  Hitoshi Ushijima

Inventor： Toshiaki Kanno ,  Makoto Katsumata ,  Hidenori Yamanashi ,  Hitoshi Ushijima

IPC: B32B15/08 ,  C25D5/54 ,  H01B1/24 ,  H01B5/14 ,  H01B13/00 ,  H05K1/09 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12 ,  H05K3/24 ,  H05K1/00

CPC classification number: H05K3/246 ,  C25D5/54 ,  H01B1/24 ,  H05K3/0014 ,  H05K3/101 ,  H05K1/095 ,  H05K2201/0129 ,  H05K2201/0323 ,  H05K2201/0347 ,  H05K2201/09118 ,  H05K2203/0113 ,  H05K3/107 ,  H05K3/12

Abstract: A conductor member for an electric circuit includes a conductive plastic mold in which carbon fibers or graphite fibers are dispersedly contained, and a metallic layer at least partially plated on the surface of said conductive plastic mold. The conductor member is provided on the surface of an insulating substrate to provide an electric circuit body. Thus, the conductor member for an electric circuit and the electric circuit body can be easily formed in a three-dimensional circuit because of its simple fabrication and excellent processing. Further, the film of metal plating can be made at a high speed and is hard to break because of the intimate contact of the plated metal.

Abstract translation: 用于电路的导体构件包括其中分散包含碳纤维或石墨纤维的导电塑料模，以及至少部分地镀在所述导电塑料模的表面上的金属层。 导体构件设置在绝缘基板的表面上，以提供电路体。 因此，由于其简单的制造和优异的加工，用于电路的导体构件和电路体可以容易地形成在三维电路中。 此外，由于电镀金属的紧密接触，可以高速地制造金属镀膜，并且难以破坏。

公开(公告)号：US5464653A

公开(公告)日：1995-11-07

申请号：US628896

申请日：1990-12-18

Applicant: Philippe Chantraine ,  Marta Zorilla

Inventor： Philippe Chantraine ,  Marta Zorilla

IPC: H01L21/768 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  B05D5/12

CPC classification number: H05K3/422 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09563 ,  H05K2203/095 ,  H05K3/0055 ,  H05K3/4644

Abstract: A method for interconnecting a multilayer metal network of an electronic circuit board is provided. In the method, the electronic circuit board is made up of a plurality of superimposed metal layers having an insulating layer disposed therebetween, wherein the material of the insulating layer is substantially inert to a catalytic activation bath and to chemical deposition of metal. A via hole is formed in the board having a first metal layer thereof as its bottom and traversing a second metal layer and using electroless deposition, metal is deposited in the via by growing the metal from the metal layers only.

Abstract translation: 提供了一种用于互连电子电路板的多层金属网络的方法。 在该方法中，电子电路板由多个重叠的金属层构成，其间具有绝缘层，绝缘层的材料对催化活化浴基本上是惰性的，并且金属的化学沉积。 在其第一金属层作为其底部并穿过第二金属层并且使用无电沉积的基板上形成通孔，仅通过从金属层生长金属而将金属沉积在通孔中。

公开(公告)号：US5450290A

公开(公告)日：1995-09-12

申请号：US195532

申请日：1994-02-14

Applicant: Christina M. Boyko ,  Francis J. Bucek ,  Richard W. Carpenter ,  Voya R. Markovich ,  Darleen Mayo ,  Cindy M. Reidsema ,  Joseph G. Sabia

Inventor： Christina M. Boyko ,  Francis J. Bucek ,  Richard W. Carpenter ,  Voya R. Markovich ,  Darleen Mayo ,  Cindy M. Reidsema ,  Joseph G. Sabia

IPC: H01B1/22 ,  H01B1/24 ,  H01L23/50 ,  H01L23/538 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H05K1/14 ,  B05D5/12 ,  H05K3/36

CPC classification number: H05K3/4069 ,  H01B1/22 ,  H01B1/24 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H05K1/095 ,  H05K1/113 ,  H05K1/167 ,  H05K3/4053 ,  H05K3/4602 ,  H01L2224/16 ,  H01L2924/15173 ,  H05K1/16 ,  H05K2201/0347 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0126 ,  H05K2203/0191 ,  H05K2203/0207 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0763 ,  H05K2203/1394 ,  H05K2203/1581 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/4644 ,  H05K3/4652 ,  Y10T29/49126

Abstract: The present invention provides an improved circuit board for mounting integrated circuit chips and a technique for manufacturing the circuit board. The board permits direct chip attachment to the circuit board by providing the necessary geometry for the footprint pattern of the chip connections without the necessity of multi-level packaging using chip carriers. The circuit board includes a substrate with plated through holes, and a film of photoresist dielectric material disposed on the substrate. The dielectric material is photo patterned to form vias which are then filled with conductive material. Electrical connection pads are formed on the exposed surface of the film of dielectric material in the pattern of the chip footprint to be mounted thereon. The vias and plated through holes are arranged in groups and patterns which provide some direct connection between the pads and plated through holes, some pads wired to vias on the exposed surface of the film of dielectric material and some vias wired to plated through holes on the surface of the substrate.

Abstract translation: 本发明提供了一种用于安装集成电路芯片的改进的电路板和用于制造电路板的技术。 该板允许通过为芯片连接的覆盖图形提供必要的几何形状，而不需要使用芯片载体的多级封装，直接芯片连接到电路板。 电路板包括具有电镀通孔的基板和设置在基板上的光致抗蚀剂介电材料的膜。 电介质材料被照片化以形成通孔，然后填充导电材料。 电连接焊盘以要安装在其上的芯片覆盖区的图案形成在介电材料膜的暴露表面上。 通孔和电镀通孔以组和图案布置，其在焊盘和电镀通孔之间提供一些直接连接，一些焊盘连接到电介质材料膜的暴露表面上的通孔，以及一些通孔连接到电镀通孔上 基板的表面。

公开(公告)号：US5407557A

公开(公告)日：1995-04-18

申请号：US201325

申请日：1994-02-24

Applicant: Atsuko Iida ,  Hiroshi Odaira ,  Yoshizumi Sato ,  Yuichi Yamamoto

Inventor： Atsuko Iida ,  Hiroshi Odaira ,  Yoshizumi Sato ,  Yuichi Yamamoto

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K1/05 ,  H05K3/02 ,  H05K3/20 ,  H05K3/24 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46 ,  C25D5/02

CPC classification number: H01L21/4857 ,  H01L23/49866 ,  H01L23/5387 ,  H05K1/056 ,  H05K3/027 ,  H05K3/242 ,  H05K3/388 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K2201/0112 ,  H05K2201/0326 ,  H05K2201/0347 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2203/107 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/4635 ,  Y10S205/917

Abstract: A multi-layer wiring board where a plurality of wiring boards are laminated. The wiring board comprises a flexible insulating layer having a through hole and a wiring pattern formed on the flexible insulating layer. The wiring pattern is composed at least of two conductive layers. The first conductive layer formed on the insulating layer is made of a non-metallic conductor and the first wiring pattern is formed by a laser beam. The second conductive layer is an electroplated layer formed on the first wiring pattern. The first and second conductive layers have different reflectance for a beam. The wiring board is manufactured by integrally laminating a plastic conductive supporting plate wound in a roll shape and an insulating film similarly wound in a roll shape; forming a through hole in a predetermined position of the insulating film; forming the first conductive layer on the laminated body provided with the through hole; forming the first wiring pattern by a laser beam; and forming the electroplated layer on the first wiring pattern.

Abstract translation: 叠层有多个布线基板的多层布线基板。 布线板包括具有通孔的柔性绝缘层和形成在柔性绝缘层上的布线图案。 布线图案至少由两个导电层组成。 形成在绝缘层上的第一导电层由非金属导体制成，并且第一布线图案由激光束形成。 第二导电层是形成在第一布线图案上的电镀层。 第一和第二导电层对于束具有不同的反射率。 通过将卷绕成卷状的塑料导电支撑板和类似地卷绕成卷状的绝缘膜整体地层叠而制造布线板; 在绝缘膜的预定位置形成通孔; 在设置有通孔的层叠体上形成第一导电层; 通过激光束形成第一布线图案; 以及在所述第一布线图案上形成所述电镀层。

公开(公告)号：US5342807A

公开(公告)日：1994-08-30

申请号：US976093

申请日：1992-11-13

Applicant: Larry D. Kinsman ,  Derek J. Gochnour ,  Alan G. Wood ,  Warren M. Farnworth

Inventor： Larry D. Kinsman ,  Derek J. Gochnour ,  Alan G. Wood ,  Warren M. Farnworth

IPC: G01R1/04 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC classification number: G01R1/0466 ,  G01R1/0483 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/85 ,  H05K3/4007 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2863 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85001 ,  H01L2224/85099 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85214 ,  H01L2225/06562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/16195 ,  H01L2924/20751 ,  H01L2924/20753 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423 ,  Y10S228/904 ,  Y10T29/49004

Abstract: On a semiconductor integrated circuit die, a semipermanent electrical connection is effected by the use of wirebond techniques, in which the parameters of the wirebond are controlled, so that less bonding force retains the leadwires to the bondpads than the attachment strength of the bondpads to the die. The wirebond techniques include attaching leadwires to bondpads on the die, using ultrasonic wedge bonding. The strength of the bond between the leadwires is significantly less than the attachment strength of the bondpads, preferably by a ratio which ensures that the bondpads are not lifted from the die when the leadwires are removed by breaking the bond between the leadwires and the bondpads. Subsequent to testing and burnin, the bond between the leadwires and the bondpads is severed. The die are then removed from the package body and the bondpads may then be attached by conventional means. The technique is useful in providing known good die.

Abstract translation: 在半导体集成电路管芯上，通过使用引线接合技术来实现半永久性电连接，其中引线键合的参数被控制，使得较少的结合力将导线保持在粘合垫上，而不是粘合垫的附着强度 死。 引线接合技术包括使用超声波楔形接合将引线连接到管芯上的焊盘。 引线之间的结合强度显着小于粘合垫的附着强度，优选地通过确保当引线通过断开引线和粘合垫之间的键而去除引线时，粘合垫不会从模具上提起的比例。 在测试和燃烧之后，引线和焊盘之间的接合被切断。 然后将模具从包装体中取出，然后可以通过常规方法将粘合垫连接起来。 该技术在提供已知的好的模具中是有用的。

公开(公告)号：US5336649A

公开(公告)日：1994-08-09

申请号：US976221

申请日：1992-11-13

Applicant: Larry D. Kinsman ,  Derek J. Gochnour ,  Alan G. Wood ,  Warren M. Farnworth

Inventor： Larry D. Kinsman ,  Derek J. Gochnour ,  Alan G. Wood ,  Warren M. Farnworth

IPC: G01R1/04 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC classification number: G01R1/0466 ,  G01R1/0483 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/85 ,  H05K3/4007 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2863 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85001 ,  H01L2224/85099 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85214 ,  H01L2225/06562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/16195 ,  H01L2924/20751 ,  H01L2924/20753 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

Abstract: In order to provide pretested bare semiconductor integrated circuit die, a temporary mechanical connection is effected by the use of a soluble material. A semipermanent electrical connection is effected, in which the parameters of the connection are controlled, so that the die remains functional subsequent to burnin and test. Subsequent to testing and burnin, the die are removed from the package body. The technique is useful in providing known good die.

Abstract translation: 为了提供预先测试的裸半导体集成电路管芯，通过使用可溶性材料实现临时机械连接。 进行半永久电连接，其中连接的参数被控制，使得模具在燃烧和测试之后保持功能。 在测试和燃烧之后，将模具从包装体中取出。 该技术在提供已知的好的模具中是有用的。