公开(公告)号：US20080308308A1

公开(公告)日：2008-12-18

申请号：US12056514

申请日：2008-03-27

Applicant: Kazuhiro Kobayashi

Inventor： Kazuhiro Kobayashi

IPC: H05K1/09 ,  H05K3/40 ,  H01L21/60

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85444 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  Y10T29/49155 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are laminated and insulating layers are laminated as a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128. A second electrode pad 132 is formed to be wider in a radial direction (a planar direction) than an outside diameter of a first electrode pad 130 on a boundary surface between a first insulating layer 121 and a second insulating layer 123. The second electrode pad 132 formed to be wider than the first electrode pad 130 is provided between the first electrode pad 130 and a via 134.

Abstract translation: 半导体器件100具有半导体芯片110被倒装安装在布线板120上的结构。布线板120具有层叠多个布线层和多​​个绝缘层的绝缘层， 层叠为第一层122，第二层124，第三层126和第四层128.第二电极焊盘132形成为在径向（平面方向）上比第一电极焊盘的外径更宽 在第一绝缘层121和第二绝缘层123之间的边界表面上形成有比第一电极焊盘130更宽的第二电极焊盘132设置在第一电极焊盘130和过孔134之间。

公开(公告)号：US20080307645A1

公开(公告)日：2008-12-18

申请号：US12047603

申请日：2008-03-13

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R43/16

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

公开(公告)号：US07458817B2

公开(公告)日：2008-12-02

申请号：US11865321

申请日：2007-10-01

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R12/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract translation: 包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机

公开(公告)号：US20080284011A1

公开(公告)日：2008-11-20

申请号：US11834696

申请日：2007-08-07

Applicant: Shyh-Ming Chang ,  Ngai Tsang ,  Kuo-Shu Kao

Inventor： Shyh-Ming Chang ,  Ngai Tsang ,  Kuo-Shu Kao

IPC: H01L23/48

CPC classification number: H01L23/49811 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13008 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09845 ,  H05K2201/09909 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A bump structure including at least one contact pad, at least one first polymer bump, at least one second polymer bump, and a conductive layer is provided. The contact pad is disposed on a substrate, and the first polymer bump is also disposed on the substrate. The second polymer bump is disposed on the substrate and is connected to the first polymer bump. The conductive layer covers the first polymer bump and electrically connects the contact pad.

Abstract translation: 提供包括至少一个接触垫，至少一个第一聚合物凸块，至少一个第二聚合物凸块和导电层的凸块结构。 接触垫设置在基板上，并且第一聚合物凸块也设置在基板上。 第二聚合物凸块设置在基板上并连接到第一聚合物凸块。 导电层覆盖第一聚合物凸块并且电连接接触垫。

公开(公告)号：US20080277141A1

公开(公告)日：2008-11-13

申请号：US11854343

申请日：2007-09-12

Applicant: Shao-Chien Lee ,  Chih-Ming Chang

Inventor： Shao-Chien Lee ,  Chih-Ming Chang

IPC: H05K1/02 ,  H05K3/20

CPC classification number: H05K3/4007 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16237 ,  H01L2224/4824 ,  H01L2924/00014 ,  H05K3/06 ,  H05K3/205 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2203/0376 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49204 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A circuit board including a dielectric layer, a circuit layer, at least one conductive joint column, and a solder mask layer is provided. The circuit layer having at least one pad is in contact with the dielectric layer. The conductive joint column is disposed on the pad. The solder mask layer is disposed on the dielectric layer and covers the circuit layer. The solder mask layer is in contact with the conductive joint column, and the conductive joint column penetrates the solder mask layer. A height of the conductive joint column is larger than a thickness of the solder mask layer. The enhanced reliability of bonding between another component and the conductive joint column will be provided. Further, a method of fabricating a circuit board is also provided.

Abstract translation: 提供了包括电介质层，电路层，至少一个导电接合柱和焊料掩模层的电路板。 具有至少一个焊盘的电路层与电介质层接触。 导电接头柱设置在垫上。 焊料掩模层设置在电介质层上并覆盖电路层。 焊接掩模层与导电接头柱接触，并且导电接头柱穿透焊接掩模层。 导电接头柱的高度大于焊料掩模层的厚度。 将提供另一部件与导电接头柱之间的接合的可靠性增强。 此外，还提供了一种制造电路板的方法。

公开(公告)号：US07449099B1

公开(公告)日：2008-11-11

申请号：US10947085

申请日：2004-09-21

Applicant: Steven T. Mayer ,  John Stephen Drewery

Inventor： Steven T. Mayer ,  John Stephen Drewery

IPC: C25D5/02

CPC classification number: H05K3/243 ,  H05K3/108 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2203/0392 ,  H05K2203/122

Abstract: To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the accelerator film remains in the recessed acceleration region. Then, metal is deposited onto the workpiece, and the metal deposits at an accelerated rate in the acceleration region, resulting in a greater thickness of metal in the acceleration region compared to metal in the non-activated field region. Then, metal is completely removed from the field region, thereby forming the metal feature.

Abstract translation: 为了制造金属特征，将不可镀层施加到工件表面，然后被图案化以形成第一镀层区域和第一非镀层区域。 然后，金属沉积在工件上，以在所述第一镀覆区域中形成凸起区域，并在所述第一非镀覆区域中形成凹陷区域。 然后，加工膜全部应用于工件上。 加速膜的一部分从场区域选择性地去除，并且加速膜的另一部分残留在凹入加速区域中。 然后，金属沉积在工件上，并且金属在加速区域中以加速的速率沉积，导致与非激活场区域中的金属相比，加速区域中的金属厚度更大。 然后，从场区域中完全去除金属，从而形成金属特征。

公开(公告)号：US20080265396A1

公开(公告)日：2008-10-30

申请号：US12164152

申请日：2008-06-30

Applicant: John J. Maloney ,  Robert M. Smith ,  Charles H. Wilson

Inventor： John J. Maloney ,  Robert M. Smith ,  Charles H. Wilson

IPC: H01L23/48

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15747 ,  H01L2924/181 ,  H05K3/341 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10689 ,  H05K2201/10727 ,  H05K2201/10969 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved.

Abstract translation: QFN封装，具有改进的焊点厚度，可提高二级附着疲劳寿命。 QFN芯片载体的铜引线框架在第二级附接之前在芯片连接焊盘区域和周围的引线区域中设置有圆形突起。 圆形的突出突起由引线框架的铜的铜本身形成。 这可以通过在电镀之前将凹坑冲压到引线框架的铜板的一个表面中以在相对表面上形成突起来实现。 形成圆形突起的这种方法简化了形成支座的过程。 突起提供了增加润湿面积的结构，并且允许使用更大量的焊料以增加焊接接​​头厚度和更好的焊盘焊接区域覆盖。 由于焊接接头厚度的增加，二级疲劳寿命显着提高。 由于焊盘焊接区域覆盖率的提高，芯片载体的热性能也得到了显着提高。

公开(公告)号：US20080257595A1

公开(公告)日：2008-10-23

申请号：US12081423

申请日：2008-04-16

Applicant: Wen-Hung Hu

Inventor： Wen-Hung Hu

IPC: H01R12/04 ,  H05K3/10

CPC classification number: H05K3/4007 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2924/00014 ,  H01L2924/14 ,  H01R12/57 ,  H05K3/06 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09745 ,  H05K2203/0353 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/01024 ,  H01L2924/01082 ,  H01L2924/01022 ,  H01L2924/01079 ,  H01L2924/01046

Abstract: The present invention relates to a packaging substrate and a method for manufacturing the same. The packaging substrate includes: a substrate body, having a plurality of conductive pads on the surface thereof, wherein the top surfaces of the conductive pads have a concave each; a solder mask, disposed on the surface of the substrate body and having a plurality of openings to correspondingly expose the concaves of the conductive pads each; and a plurality of metal bumps, disposed correspondingly in the openings of the solder mask and over the concaves of the conductive pads. The present invention increases the joint surface area between the metal bumps and the conductive pads so as to inhibit the joint crack and improve the reliability of the conductive structure of the packaging substrate.

Abstract translation: 本发明涉及一种包装基板及其制造方法。 封装基板包括：基板主体，其表面上具有多个导电焊盘，其中导电焊盘的顶表面各具有凹面; 焊接掩模，设置在基板主体的表面上并且具有多个开口以相应地暴露每个导电焊盘的凹部; 以及多个金属凸块，相应地设置在焊料掩模的开口中并在导电焊盘的凹部之上。 本发明增加了金属凸块和导电焊盘之间的接合表面积，从而抑制接头裂纹，提高了封装基板的导电结构的可靠性。

公开(公告)号：US20080254611A1

公开(公告)日：2008-10-16

申请号：US12100380

申请日：2008-04-09

Applicant: TERRY LEE STERRETT ,  RICHARD J. HARRIES

Inventor： TERRY LEE STERRETT ,  RICHARD J. HARRIES

IPC: H01L21/44

CPC classification number: H01L24/14 ,  B29C39/026 ,  B29C70/58 ,  B29C70/882 ,  B29L2031/3406 ,  C08J5/10 ,  C08L101/12 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K3/321 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2201/10719 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2224/05099

Abstract: Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter.

Abstract translation: 公开了用于增加互连凸块的互连区域的方法和设计。 互连凸块可以形成在衬底上，使得互连凸块延伸超过接触焊盘到衬底上。 可以在更大的接触焊盘上形成互连凸块，凸块具有大直径。

公开(公告)号：US20080235941A1

公开(公告)日：2008-10-02

申请号：US11694913

申请日：2007-03-30

Applicant: Seng Guan Chow

Inventor： Seng Guan Chow

IPC: H05K3/34

CPC classification number: H05K3/284 ,  H01L2224/32225 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/19105 ,  H05K1/111 ,  H05K3/1216 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4007 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/10636 ,  H05K2201/10992 ,  H05K2203/043 ,  H05K2203/1476 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2924/00

Abstract: An integrated circuit package system is provided including providing a substrate having a contact pad, forming a first conductor having a first melting point over the contact pad, forming a second conductor having a second melting point over the first conductor with the first melting point higher than the second melting point, and mounting a first device over the second conductor.

Abstract translation: 提供了一种集成电路封装系统，包括提供具有接触焊盘的衬底，形成在接触焊盘上具有第一熔点的第一导体，在第一导体上形成具有第二熔点的第二导体，第一熔点高于 第二熔点，并且将第一装置安装在第二导体上。