公开(公告)号：US5606452A

公开(公告)日：1997-02-25

申请号：US548034

申请日：1995-10-25

Applicant: Yong-Ki Min

Inventor： Yong-Ki Min

IPC: G02B5/09 ,  B81B3/00 ,  G02B5/10 ,  G02B7/18 ,  G02B26/08 ,  G09F9/37 ,  H04N5/74 ,  H04N9/30 ,  G02B26/00

CPC classification number: B81C1/00214 ,  B81C1/00174 ,  G02B26/0858 ,  H04N9/30 ,  B81B2201/032 ,  B81B2201/042 ,  B81C2201/0109

Abstract: An array of M.times.N thin film actuated mirrors includes an active matrix having a substrate with an array of M.times.N connecting terminals and an array of M.times.N transistors, and an array of M.times.N actuating structures, wherein each of the actuating structures being a bimorph structure, includes a second thin film electrode, a lower electrodisplacive member, an intermediate thin film electrode, an upper electrodisplacive member and a first thin film electrode. Furthermore, there is disclosed a method for the manufacture thereof, the method comprising the steps of: providing an active matrix; forming a thin film sacrificial layer on top of the active matrix; removing selectively the thin film sacrificial layer; forming a second thin film electrode layer thereon; removing selectively the second thin film electrode layer; depositing a lower electrodisplacive layer; forming an intermediate electrode layer; depositing an upper electrodisplacive layer; forming a first thin film electrode layer, thereby forming a multiple layered structure; patterning the multiple layered structure into an array of M.times.N semifinished actuating structures; and removing the thin film sacrificial layer.

Abstract translation: MxN薄膜致动反射镜阵列包括具有MxN连接端子阵列和MxN晶体管阵列的衬底以及MxN致动结构阵列的有源矩阵，其中每个致动结构是双压电晶片结构，包括一个 第二薄膜电极，下电致位移元件，中间薄膜电极，上部电致位移元件和第一薄膜电极。 此外，公开了一种制造方法，该方法包括以下步骤：提供有源矩阵; 在有源矩阵的顶部形成薄膜牺牲层; 选择性地去除薄膜牺牲层; 在其上形成第二薄膜电极层; 选择性地去除第二薄膜电极层; 沉积较低的电致位移层; 形成中间电极层; 沉积上部电致位移层; 形成第一薄膜电极层，从而形成多层结构; 将多层结构图案化成MxN半成品致动结构的阵列; 并去除薄膜牺牲层。

公开(公告)号：US5578755A

公开(公告)日：1996-11-26

申请号：US348700

申请日：1994-12-02

Applicant: Michael Offenberg

Inventor： Michael Offenberg

IPC: B81B3/00 ,  G01P15/08 ,  G01P15/125 ,  H01L49/00

CPC classification number: B81B3/0086 ,  B81B3/0035 ,  B81B3/0078 ,  B81C1/00595 ,  G01P15/0802 ,  G01P15/125 ,  B81B2201/0235 ,  B81B2203/0118 ,  B81B2203/0136 ,  B81C2201/0107 ,  B81C2201/0109 ,  B81C2201/016 ,  G01P2015/0814

Abstract: In an accelerometer sensor of crystalline material, whose components are composed partly of monocrystalline and partly of polycrystalline material, a band-shaped seismic mass preferably is composed of polycrystalline material, whose suspension by means of suspension segments of monocrystalline material at the end regions permits a movement in the longitudinal direction upon the occurrence of an acceleration. Parallel plates extend from this mass at right angles to their longitudinal direction and, together with additional plates, which run parallel to said plates and are anchored at a base, form a capacitor arrangement and are composed, in particular, of monocrystalline material. At least the monocrystalline material is doped to attain an electric conductivity. When lightly doped, the long and thin plates and suspension segments have a high conductivity, given a very small mechanical prestressing, and can easily be isotropically undercut. The polycrystalline formation of the seismic mass can be designed to be very wide and large by etching away an underlying sacrificial oxide.

Abstract translation: 在结晶材料的加速度传感器中，其部件部分由单晶组成，部分由多晶材料组成，带状地震质量体优选地由多晶材料组成，其结晶区域的单晶材料悬浮段的悬浮液允许 发生加速时的纵向移动。 平行板从该质量块垂直于其纵向方向延伸，并且与另外的板一起平行于所述板并锚定在基座上，形成电容器布置，并且特别地由单晶材料组成。 至少单晶材料被掺杂以获得导电性。 当轻掺杂时，长且薄的板和悬浮段具有高导电性，给定非常小的机械预应力，并且可以容易地各向同性地切削。 通过蚀刻掉潜在的牺牲氧化物，可以将地震块的多晶形成设计得非常宽和大。

公开(公告)号：US11952268B2

公开(公告)日：2024-04-09

申请号：US17304094

申请日：2021-06-14

Applicant: Lawrence Semiconductor Research Laboratory, Inc.

Inventor： Chantal Arena ,  Nupur Bhargava ,  Alec Fischer

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00476 ,  B81B3/0072 ,  B81B2203/0118 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0177

Abstract: A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.

公开(公告)号：US11946822B2

公开(公告)日：2024-04-02

申请号：US17290140

申请日：2019-10-16

Applicant: Sciosense B.V.

Inventor： Alessandro Faes ,  Jörg Siegert ,  Willem Frederik Adrianus Besling ,  Remco Henricus Wilhelmus Pijnenburg

IPC: G01L9/00 ,  B81B3/00 ,  B81C1/00

CPC classification number: G01L9/0073 ,  B81B3/0021 ,  B81C1/00595 ,  G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/015 ,  B81C2201/0109 ,  B81C2201/0133 ,  B81C2201/014

Abstract: In an embodiment a semiconductor transducer device includes a semiconductor body and a diaphragm having a first layer and a second layer, wherein a main extension plane of the diaphragm is arranged parallel to a surface of the semiconductor body, wherein the diaphragm is suspended at a distance from the semiconductor body in a direction perpendicular to the main extension plane of the diaphragm, wherein the second layer comprises titanium and/or titanium nitride, wherein the first layer comprises a material that is resistant to an etchant comprising fluorine or a fluorine compound, and wherein the second layer is arranged between the semiconductor body and the first layer.

公开(公告)号：US20240100566A1

公开(公告)日：2024-03-28

申请号：US18530629

申请日：2023-12-06

Applicant: BFLY OPERATIONS, INC.

Inventor： Lingyun Miao ,  Keith G. Fife ,  Jianwei Liu ,  Jonathan M. Rothberg

IPC: B06B1/02 ,  B81B3/00 ,  B81C1/00

CPC classification number: B06B1/0292 ,  B81B3/001 ,  B81C1/00984 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0392 ,  B81C2201/0109 ,  B81C2201/0125 ,  B81C2201/0176

Abstract: An ultrasound transducer device made by a process that includes the steps of forming depositing a first layer on a substrate, depositing a second layer on the first layer, patterning the second layer at a region corresponding to a location of a transducer cavity, depositing a third layer that refills regions created by patterning the second layer, planarizing the third layer to a top surface of the second layer, removing the second layer, conformally depositing a fourth layer over the first layer and the third layer, defining the transducer cavity in a support layer formed over the fourth layer; and bonding a membrane to the support layer.

公开(公告)号：US20230382717A1

公开(公告)日：2023-11-30

申请号：US18448600

申请日：2023-08-11

Applicant: ROHM CO., LTD.

Inventor： Martin Wilfried HELLER

IPC: B81B3/00 ,  B81C1/00 ,  G01P15/125

CPC classification number: B81B3/0051 ,  B81C1/00341 ,  G01P15/125 ,  B81B2201/0235 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C2201/0109 ,  B81C2201/0132

Abstract: A MEMS sensor includes a semiconductor chip that has a first principal surface and a second principal surface and that has a cavity, a frame portion that forms a bottom portion and a side portion of the cavity, and a movable portion that is formed on the side of the first principal surface and that is supported by the frame portion in a floating state with respect to the cavity, and, in the MEMS sensor, the frame portion has a stepped surface formed at a height position between the bottom portion of the cavity and the first principal surface, and the movable portion includes a main body portion facing the cavity in a first direction and an extension portion that extends from the main body portion toward an upper region of the stepped surface in a second direction and that faces the stepped surface in the first direction.

公开(公告)号：US11759823B2

公开(公告)日：2023-09-19

申请号：US16936452

申请日：2020-07-23

Applicant: Vanguard International Semiconductor Corporation

Inventor： You Qian ,  Rakesh Kumar ,  Jia Jie Xia

IPC: B06B1/06 ,  B81B3/00 ,  B81C1/00

CPC classification number: B06B1/0666 ,  B81B3/0021 ,  B81C1/00158 ,  B81B2201/0271 ,  B81B2203/0127 ,  B81B2203/0307 ,  B81B2203/04 ,  B81C2201/0109

Abstract: A PMUT includes a substrate, a membrane, and a sacrificial layer. The substrate has a cavity penetrating the substrate. The membrane is disposed over the cavity and includes a first piezoelectric layer, a bottom electrode, a top electrode, and a second piezoelectric layer. The first piezoelectric layer is disposed over the cavity and includes an anchor portion, where the anchor portion of the first piezoelectric layer is in direct contact with the substrate. The top and bottom electrodes are disposed over the first piezoelectric layer. The second piezoelectric layer is disposed between the bottom electrode and the top electrode. The sacrificial layer is disposed between the substrate and the first piezoelectric layer, and a vertical projection of the sacrificial layer does not overlap a vertical projection of portions of the membrane disposed over the cavity.

公开(公告)号：US11708262B2

公开(公告)日：2023-07-25

申请号：US17687230

申请日：2022-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yi-Hsien Chang ,  Chun-Ren Cheng ,  Wei-Cheng Shen ,  Wen-Chien Chen

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0072 ,  B81B3/0013 ,  B81C1/00476 ,  B81C1/00666 ,  B81C1/00968 ,  B81C1/00984 ,  B81B2201/0257 ,  B81B2207/012 ,  B81C2201/0105 ,  B81C2201/017 ,  B81C2201/0109 ,  B81C2201/0128 ,  B81C2201/0147 ,  B81C2201/0163 ,  B81C2201/053 ,  B81C2203/0792 ,  H04R2201/003

Abstract: A method of manufacturing a semiconductor structure includes following operations. A first substrate is provided. A plate is formed over the first substrate. The plate includes a first tensile member, a second tensile member, a semiconductive member between the first tensile member and the second tensile member, and a plurality of apertures penetrating the first tensile member, the semiconductive member and the second tensile member. A membrane is formed over and separated from the plate. The membrane include a plurality of holes. A plurality of conductive plugs passing through the plate or membrane are formed. A plurality of semiconductive pads are formed over the plurality of conductive plugs. The plate is bonded to a second substrate. The second substrate includes a plurality of bond pads, and the semiconductive pads are in contact with the bond pads.

公开(公告)号：US20230149976A1

公开(公告)日：2023-05-18

申请号：US18093701

申请日：2023-01-05

Applicant: BFLY OPERATIONS, INC.

Inventor： Lingyun Miao ,  Keith G. Fife ,  Jianwei Liu ,  Jonathan M. Rothberg

IPC: B06B1/02 ,  B81B3/00 ,  B81C1/00

CPC classification number: B06B1/0292 ,  B81B3/001 ,  B81C1/00984 ,  B81B2203/0315 ,  B81C2201/0176 ,  B81B2203/0127 ,  B81C2201/0109 ,  B81C2201/0125 ,  B81B2203/0392

Abstract: A method of forming an ultrasonic transducer device involves depositing a first layer on a substrate, depositing a second layer on the first layer, patterning the second layer at a region corresponding to a location of a transducer cavity, depositing a third layer that refills regions created by patterning the second layer, planarizing the third layer to a top surface of the second layer, removing the second layer, conformally depositing a fourth layer over the first layer and the third layer, defining the transducer cavity in a support layer formed over the fourth layer; and bonding a membrane to the support layer.

公开(公告)号：US20190017189A1

公开(公告)日：2019-01-17

申请号：US16118267

申请日：2018-08-30

Applicant: Microfabrica Inc.

Inventor： Adam L. Cohen ,  Michael S. Lockard ,  Kieun Kim ,  Qui T. Le ,  Gang Zhang ,  Uri Frodis ,  Dale S. McPherson ,  Dennis R. Smalley

IPC: C25D5/02 ,  C23C18/16 ,  C25D1/00 ,  B81C1/00

CPC classification number: C25D5/022 ,  B81C1/00126 ,  B81C2201/0109 ,  B81C2201/019 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  Y10T156/11 ,  Y10T156/19

Abstract: Some embodiments are directed to techniques for building single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while others use an intervening adhesion layer material. Some embodiments use different seed layer and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while others apply the materials in blanket fashion. Some embodiments remove extraneous material via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer.