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    Monolithic CMOS-MEMS microphones and method of manufacturing
    161.
    发明授权
    Monolithic CMOS-MEMS microphones and method of manufacturing 有权
    单片CMOS-MEMS麦克风及其制造方法

    公开(公告)号：US09481569B2

    公开(公告)日：2016-11-01

    申请号：US14888606

    申请日：2014-05-02

    Applicant: Robert Bosch GmbH

    Inventor： John Zinn ,  Brett Diamond ,  Jochen Hoffmann

    IPC: B81C1/00 ,  H04R31/00

    CPC classification number: B81C1/00246 ,  B81B2201/0257 ,  B81C2201/0132 ,  H04R31/00 ,  H04R31/003 ,  H04R2201/003

    Abstract: Systems and methods are disclosed for manufacturing a CMOS-MEMS device (100). A partial protective layer (401) is deposited on a top surface of a layered structure to cover a circuit region. A first partial etch is performed from the bottom side of the layered structure to form a first gap (501) below a MEMS membrane (207) within a MEMS region of the layered structure. A second partial etch is performed from the top side of the layered structure to remove a portion of a sacrificial layer between the MEMS membrane and a MEMS backplate (215) within the MEMS region. The second partial etch releases the MEMS membrane so that it can move in response to pressures. The deposited partial protective layer prevents the second partial etch from etching a portion of the sacrificial layer positioned within the circuit region of the layered structure and also prevents the second partial etch from damaging the CMOS circuit component (211).

    Abstract translation: 公开了用于制造CMOS-MEMS器件（100）的系统和方法。 部分保护层（401）沉积在层状结构的顶表面上以覆盖电路区域。 从分层结构的底侧执行第一部分蚀刻，以在分层结构的MEMS区域内的MEMS膜（207）下方形成第一间隙（501）。 从分层结构的顶侧执行第二部分蚀刻以去除MEMS区域内的MEMS膜与MEMS背板（215）之间的牺牲层的一部分。 第二部分蚀刻释放MEMS膜，使得其可以响应于压力移动。 沉积的部分保护层防止第二部分蚀刻蚀刻位于层状结构的电路区域内的牺牲层的一部分，并且还防止第二部分蚀刻损坏CMOS电路部件（211）。

    Semiconductor device having a micro-mechanical structure
    162.
    发明授权
    Semiconductor device having a micro-mechanical structure 有权
    具有微机械结构的半导体器件

    公开(公告)号：US09481563B2

    公开(公告)日：2016-11-01

    申请号：US14644937

    申请日：2015-03-11

    Applicant: Infineon Technologies AG

    Inventor： Manfred Engelhardt ,  Martin Zgaga

    IPC: B81B3/00 ,  B81C1/00

    CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a micro-mechanical structure and a semiconductor material arranged over the micro-mechanical structure. A side surface of the semiconductor material includes a first region and a second region. The first region has an undulation, and the second region is a peripheral region of the side surface and decreases towards the micro-mechanical structure.

    Abstract translation: 根据半导体器件的实施例，半导体器件包括布置在微机械结构上的微机械结构和半导体材料。 半导体材料的侧表面包括第一区域和第二区域。 第一区域具有起伏，第二区域是侧表面的周边区域，朝向微机械结构减小。

    Epi-poly etch stop for out of plane spacer defined electrode
    163.
    发明授权
    Epi-poly etch stop for out of plane spacer defined electrode 有权
    用于外平面间隔物限定电极的Epi-多晶蚀刻停止

    公开(公告)号：US09469522B2

    公开(公告)日：2016-10-18

    申请号：US14201453

    申请日：2014-03-07

    Applicant: Robert Bosch GmbH

    Inventor： Andrew Graham ,  Gary Yama ,  Gary O'Brien

    IPC: B81C1/00 ,  B81B3/00

    CPC classification number: B81B3/0021 ,  B81B2201/0271 ,  B81B2203/04 ,  B81B2203/053 ,  B81C1/00095 ,  B81C1/00166 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/0177 ,  B81C2203/0136

    Abstract: In one embodiment, a method of forming an out-of-plane electrode includes forming an oxide layer above an upper surface of a device layer, etching an etch stop perimeter defining trench extending through the oxide layer, forming a first cap layer portion on an upper surface of the oxide layer and within the etch stop perimeter defining trench, etching a first electrode perimeter defining trench extending through the first cap layer portion and stopping at the oxide layer, depositing a first material portion within the first electrode perimeter defining trench, depositing a second cap layer portion above the deposited first material portion, and vapor releasing a portion of the oxide layer with the etch stop portion providing a lateral etch stop.

    Abstract translation: 在一个实施例中，形成平面外电极的方法包括在器件层的上表面上形成氧化物层，蚀刻限定延伸穿过氧化物层的沟槽的蚀刻停止周界，在第一帽层部分上形成 氧化物层的上表面，并且在蚀刻停止周界内限定沟槽，蚀刻延伸穿过第一盖层部分并停止在氧化物层处的第一电极周界，限定沟槽，在第一电极周界限定沟槽内沉积第一材料部分，沉积 在沉积的第一材料部分上方的第二盖层部分，以及用蚀刻停止部分提供横向蚀刻停止物的一部分氧化物层的蒸气。

    METHOD OF FABRICATING A MEMS DEVICE
    164.
    发明申请
    METHOD OF FABRICATING A MEMS DEVICE 有权
    制造MEMS器件的方法

    公开(公告)号：US20160299334A1

    公开(公告)日：2016-10-13

    申请号：US14685099

    申请日：2015-04-13

    Applicant: Texas Instruments Incorporated

    Inventor： Sean Christopher O'Brien

    IPC: G02B26/08 ,  G03F7/00

    CPC classification number: G02B26/0833 ,  B81B2201/042 ,  B81C1/00809 ,  B81C2201/0132 ,  G03F7/26

    Abstract: A microelectromechanical system (MEMS) is comprised of a micromirror device attached to a semiconductor device. A first spacer layer is formed and patterned to form hinge via openings. A hinge metal is deposited above the first spacer layer to form the hinge and the hinge vias. A capping layer is formed above the hinge metal and hinge vias. A second spacer layer is formed above the capping layer and patterned to form a mirror via. The capping layer protects the hinge metal from the developer solution used in the patterning step. The capping layer is removed from within the mirror via opening. Another metal layer is deposited above the second spacer layer to form the mirror and the mirror via.

    Abstract translation: 微机电系统（MEMS）由附接到半导体器件的微镜器件组成。 形成第一间隔层并图案化以形成铰链通孔。 铰链金属沉积在第一间隔层上方以形成铰链和铰链通孔。 在铰链金属和铰链通孔上方形成覆盖层。 在封盖层上方形成第二间隔层并图案化以形成反射镜。 封盖层保护铰链金属免受图案化步骤中使用的显影剂溶液的影响。 通过打开将覆盖层从反射镜中去除。 另一金属层沉积在第二间隔层上方以形成反射镜和反射镜。

    MEMS method and structure
    167.
    发明授权
    MEMS method and structure 有权
    MEMS方法和结构

    公开(公告)号：US09394164B2

    公开(公告)日：2016-07-19

    申请号：US13827928

    申请日：2013-03-14

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ting-Hau Wu ,  Kuei-Sung Chang

    IPC: B81C1/00

    CPC classification number: B81C1/00801 ,  B81B3/0021 ,  B81B2201/0235 ,  B81B2207/012 ,  B81B2207/015 ,  B81C1/00587 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/036

    Abstract: MEMS structures and methods utilizing a locker film are provided. In an embodiment a locker film is utilized to hold and support a moveable mass region during the release of the moveable mass region from a surrounding substrate. By providing additional support during the release of the moveable mass, the locker film can reduce the amount of undesired movement that can occur during the release of the moveable mass, and preventing undesired etching of the sidewalls of the moveable mass.

    Abstract translation: 提供了使用更衣室膜的MEMS结构和方法。 在一个实施例中，使用更衣膜来在可移动质量区域与周围基底的释放期间保持和支撑可移动质量区域。 通过在可移动质量块的释放期间提供额外的支撑，更衣室膜可以减少在可移动质量块的释放期间可能发生的不期望的运动的量，并且防止可移动质量块的侧壁的不期望的蚀刻。

    METHOD FOR MANUFACTURING ELECTRONIC COMPONENT
    168.
    发明申请
    METHOD FOR MANUFACTURING ELECTRONIC COMPONENT 有权
    制造电子元件的方法

    公开(公告)号：US20160200569A1

    公开(公告)日：2016-07-14

    申请号：US15077188

    申请日：2016-03-22

    Applicant: SUMITOMO PRECISION PRODUCTS CO., LTD.

    Inventor： Yasuyuki HIRATA ,  Gen MATSUOKA

    IPC: B81C1/00

    CPC classification number: B81C1/00492 ,  B81B3/0086 ,  B81B2201/042 ,  B81B2203/0136 ,  B81C1/00404 ,  B81C1/00603 ,  B81C2201/0102 ,  B81C2201/0132 ,  B81C2201/0198 ,  G02B26/0841

    Abstract: At the first etching step of etching an SOI substrate from a first silicon layer side, a portion of a first structure formed of the first silicon layer is formed as a pre-structure having a larger shape than a final shape. At the mask formation step of forming a final mask on a second silicon layer side of the SOI substrate, a first mask corresponding to the final shape of the first structure is formed in the pre-structure. At the second etching step of etching the SOI substrate from the second silicon layer side, the second silicon layer and the pre-structure are, using the first mask, etched to form the final shape of the first structure.

    Abstract translation: 在从第一硅层侧蚀刻SOI衬底的第一蚀刻步骤中，由第一硅层形成的第一结构的一部分形成为具有比最终形状更大的形状的预结构。 在SOI衬底的第二硅层侧形成最终掩模的掩模形成步骤中，在预结构中形成对应于第一结构的最终形状的第一掩模。 在从第二硅层侧蚀刻SOI衬底的第二蚀刻步骤中，使用第一掩模蚀刻第二硅层和预制结构以形成第一结构的最终形状。

    Estimation of sidewall skew angles of a structure
    169.
    发明授权
    Estimation of sidewall skew angles of a structure 有权
    一种结构侧壁倾斜角的估计

    公开(公告)号：US09316665B2

    公开(公告)日：2016-04-19

    申请号：US13867720

    申请日：2013-04-22

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： Aaron A. Geisberger ,  Kemiao Jia

    IPC: G01N3/20 ,  G01P15/08 ,  G01C19/5656 ,  G01C19/5663 ,  G01C25/00 ,  G01B5/24 ,  B81C99/00

    CPC classification number: G01P15/0888 ,  B81C99/004 ,  B81C2201/0132 ,  G01B5/24 ,  G01C19/5656 ,  G01C19/5663 ,  G01C25/005

    Abstract: An apparatus (36) includes a motion amplification structure (52), an actuator (54), and a sense electrode (50) in proximity to the structure (52). The actuator (54) induces an axial force (88) upon the structure (52), which causes a relatively large amount of in-plane motion (108) in one or more beams (58, 60) of the structure (52). When sidewalls (98) of the beams (58, 60) exhibit a skew angle (28), the in-plane motion (108) of the beams (58, 60) produces out-of-plane motion (110) of a paddle element (62) connected to the end of the beams (58, 60). The skew angle (28), which results from an etch process, defines a degree to which the sidewalls (98) of beams (58, 60) are offset or tilted from their design orientation. The out-of-plane motion (110) of element (62) is sensed at the electrode (50), and is utilized to determine an estimated skew angle (126).

    Abstract translation: 装置（36）包括靠近结构（52）的运动放大结构（52），致动器（54）和感测电极（50）。 致动器（54）在结构（52）上引起轴向力（88），其在结构（52）的一个或多个梁（58,60）中引起相对大量的平面内运动（108）。 当梁（58,60）的侧壁（98）呈现偏斜角（28）时，梁（58,60）的平面内运动（108）产生桨叶的平面外运动（110） 元件（62）连接到梁（58,60）的端部。 由蚀刻工艺产生的偏斜角（28）限定了梁（58,60）的侧壁（98）从其设计取向偏移或倾斜的程度。 在电极（50）处感测元件（62）的平面外运动（110），并用于确定估计的倾斜角（126）。

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