公开(公告)号：US20030219956A1

公开(公告)日：2003-11-27

申请号：US10445330

申请日：2003-05-27

Applicant: NEC CORPORATION

Inventor： Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi

IPC: H01L021/20 ,  H01L029/00 ,  H05K001/16

CPC classification number: H05K1/162 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H05K1/185 ,  H05K3/429 ,  H05K2201/0317 ,  H05K2201/09509

Abstract: A thin film capacitor is provided with a substrate having a thickness equal to or more than 2 nullm and equal to or less than 100 nullm; a lower electrode on the substrate, which includes at least a highly elastic electrode and an anti-oxidation electrode on the highly elastic electrode; a dielectric thin film on the first lower electrode; and an upper electrode on the dielectric thin film; wherein the highly elastic electrode is made of a material having a Young's modulus higher than that of the anti-oxidation electrode.

Abstract translation: 薄膜电容器具有厚度等于或大于2μm且等于或小于100μm的基板; 所述基板上的下部电极，在所述高弹性电极上至少包括高弹性电极和抗氧化电极; 第一下电极上的电介质薄膜; 和电介质薄膜上的上电极; 其中所述高弹性电极由杨氏模量高于所述抗氧化电极的杨氏模量的材料制成。

公开(公告)号：US20030203101A1

公开(公告)日：2003-10-30

申请号：US10422557

申请日：2003-04-23

Applicant: SiPix Imaging, Inc.

Inventor： Jeanne E. Haubrich ,  Y. S. Chaug ,  Zarng-Arh George Wu ,  Abbas Hosseini ,  Paul Gendler ,  Rong-Chang Liang

IPC: B05D005/12 ,  C25D005/02

CPC classification number: G02F1/13439 ,  H05K3/04 ,  H05K3/048 ,  H05K3/146 ,  H05K3/16 ,  H05K3/184 ,  H05K3/386 ,  H05K2201/0317 ,  H05K2203/0257 ,  H05K2203/0264 ,  H05K2203/0522 ,  H05K2203/0746

Abstract: A process for forming a patterned conductive structure on a substrate is disclosed. A pattern is printed with a material, such as a masking coating or an ink, on the substrate, the pattern being such that, in one embodiment, the desired conductive structures will be formed in the areas where the printed material is not present, i.e., a negative image of conductive structure to be formed is printed. In another embodiment, the pattern is printed with a material that is difficult to strip from the substrate, and the desired conductive structures will be formed in the areas where the printed material is present, i.e., a positive image of the conductive structure is printed. The conductive material is deposited on the patterned substrate, and the undesired area is stripped, leaving behind the patterned electrode structures.

Abstract translation: 公开了一种在衬底上形成图案化导电结构的工艺。 在衬底上印有诸如掩模涂层或墨水的材料的图案，该图案使得在一个实施例中，将在不存在印刷材料的区域中形成所需的导电结构，即 印刷要形成的导电结构的负像。 在另一个实施例中，图案用难以从衬底剥离的材料印刷，并且所需的导电结构将形成在印刷材料存在的区域中，即印刷导电结构的正像。 导电材料沉积在图案化的衬底上，并且不期望的区域被剥离，留下图案化的电极结构。

公开(公告)号：US20030136814A1

公开(公告)日：2003-07-24

申请号：US10052591

申请日：2002-01-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce Kenneth Furman ,  Maheswaran Surendra ,  Sherif A. Goma ,  Simon M. Karecki ,  John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker ,  Anna Karecki

IPC: B23K031/02

CPC classification number: H01L24/12 ,  H01L21/288 ,  H01L21/2885 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13582 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2224/45111 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, some of which may be selected to have similar interconnect structures so as to form all together an assembled carrier that functions as a complete computing, communications or networking system.

Abstract translation: 一个微型接头互连结构，包括具有精确可控高度的密集阵列的金属螺柱，并具有接合冶金。 该阵列在要连接到载体的装置芯片上或与其他装置一起在载体上产生，其中一些装置芯片可被选择为具有相似的互连结构，以便将组装的载体形成为一体， 完整的计算，通信或网络系统。

公开(公告)号：US06596391B2

公开(公告)日：2003-07-22

申请号：US09075732

申请日：1998-05-11

Applicant: Gordon C. Smith

Inventor： Gordon C. Smith

IPC: B32B1504

CPC classification number: B32B15/08 ,  B32B7/06 ,  B32B7/12 ,  B32B2307/202 ,  B32B2457/08 ,  H05K3/025 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2203/0769 ,  H05K2203/0786 ,  Y10S428/901 ,  Y10T428/12556 ,  Y10T428/12569 ,  Y10T428/265 ,  Y10T428/2804 ,  Y10T428/2839 ,  Y10T428/31678 ,  Y10T428/31692

Abstract: Disclosed is a metal-clad laminate product having a carrier film, a aqueous soluble release or parting layer deposited onto the carrier film and which can be mechanically separated from the carrier film, and an ultra thin metal layer deposited onto the parting layer. Also disclosed is a method for making the metal-clad laminate product.

公开(公告)号：US20030110629A1

公开(公告)日：2003-06-19

申请号：US10034030

申请日：2001-12-19

Inventor： Gwo-Ji Horng ,  Jen-I Kuo ,  Feng-Ger Hsiau

IPC: H05K013/00 ,  H05K003/36

CPC classification number: H01L24/32 ,  H01L21/4857 ,  H01L23/3677 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15787 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4053 ,  H05K3/4605 ,  H05K3/4629 ,  H05K3/4679 ,  H05K2201/0317 ,  H05K2201/09063 ,  H05K2203/166 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2924/00

Abstract: A method of fabricating a thermal conductive plug of a ceramic substrate of a multi-chip package. A plurality of conductive openings and thermal conductive openings are formed on green tapes. A metal paste is filled into the conductive openings and the thermal conductive openings. The green tapes are stacked together so that the metal paste inside the conductive openings and the thermal conductive openings of every green tape is in contact respectively with its neighboring metal paste within the conductive openings and thermal conductive openings of the green tapes. Cofire those green tapes and the metal paste to form a pre-substrate. The pre-substrate comprises an insulating structure, a plurality of thermal conductive plugs and conductive plugs.

Abstract translation: 一种制造多芯片封装的陶瓷衬底的导热插塞的方法。 在绿色带上形成多个导电开口和导热开口。 将金属膏填充到导电开口和导热开口中。 生带被堆叠在一起，使得导电开口内的金属膏和每个生带的导热开口分别与导电开口内的相邻金属膏和生带的导热开口接触。 将这些绿色胶带和金属糊料烧结以形成预底物。 预衬底包括绝缘结构，多个导热插塞和导电插头。

公开(公告)号：US06565917B1

公开(公告)日：2003-05-20

申请号：US09525472

申请日：2000-03-15

Applicant: Srinivasa S. N. Reddy ,  Donald R. Wall

Inventor： Srinivasa S. N. Reddy ,  Donald R. Wall

IPC: B05D512

CPC classification number: H05K3/246 ,  C04B41/009 ,  C04B41/52 ,  C04B41/89 ,  C04B2111/00844 ,  H01L23/49883 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/245 ,  H05K3/4061 ,  H05K2201/0317 ,  H05K2201/0347 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/265 ,  C04B41/4539 ,  C04B41/4572 ,  C04B41/5031 ,  C04B41/5041 ,  C04B41/5042 ,  C04B41/5144 ,  C04B35/00 ,  H01L2924/00

Abstract: A paste for one of a via and an external feature, such as a pad, tab, or line, of a ceramic substrate, includes at least one of titania and zirconia, and a filler material mixed with the at least one of titania and zirconia. Further, the via structure or external feature such as an input/output pad, tab, or line, includes a metallic plating thereover. A method of forming the via structure or the external feature on the ceramic substrate, includes steps of either depositing the paste in the via of the ceramic substrate or depositing the paste on the ceramic substrate, and depositing, by a dry process metallic plating, a metallic plating on the paste. The paste includes at least one of titania and zirconia for reducing residual stress without effecting the platability of the metallic plating.

Abstract translation: 用于陶瓷基板的通孔和外部特征（例如垫，突片或线）之一的糊料包括二氧化钛和氧化锆中的至少一种，以及与二氧化钛和氧化锆中的至少一种混合的填充材料 。 此外，通孔结构或诸如输入/输出焊盘，突片或线的外部特征包括其上的金属电镀。 在陶瓷基板上形成通孔结构或外部特征的方法包括以下步骤：将糊料沉积在陶瓷基板的通孔中或将该糊料沉积在陶瓷基板上，并通过干法金属镀层沉积 金属电镀在糊状物上。 糊料包括二氧化钛和氧化锆中的至少一种，用于降低残余应力而不影响金属镀层的镀层。

公开(公告)号：US20030049166A1

公开(公告)日：2003-03-13

申请号：US10038276

申请日：2002-01-02

Inventor： Shaun Pendo ,  Rajiv Shah ,  Edward Chernoff

IPC: G01N027/00

CPC classification number: H05K3/28 ,  A61B5/0006 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2203/082 ,  H05K2203/085 ,  H05K2203/1147 ,  H05K2203/1476 ,  H05K2203/1572 ,  H05K2203/308

Abstract: A substrate with hermetically sealed vias extending from one side of the substrate to another and a method for fabricating same. The vias may be filled with a conductive material such as, for example, a fritless ink. The conductive path formed by the conductive material aids in sealing one side of the substrate from another. One side of the substrate may include a sensing element and another side of the substrate may include sensing electronics.

公开(公告)号：US06476695B1

公开(公告)日：2002-11-05

申请号：US09578691

申请日：2000-05-26

Applicant: Masumi Nakamichi

Inventor： Masumi Nakamichi

IPC: H01P308

CPC classification number: H05K1/167 ,  H05K1/0237 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2201/10045 ,  H05K2203/1461

Abstract: A high frequency module is provided with a resistor array layer with interconnections, in which a plurality of resistor elements having a prescribed resistance value are formed as an array, and in which an interconnection pattern for providing electrical connection to each resistor element is formed in advance. Additionally, a capacitor array layer with interconnection in which a plurality of capacitor elements having a prescribed capacitance value are formed as an array and an interconnection pattern for providing electrical connection to each capacitor element is also formed in advance for later use. A desired circuit constant is obtained by providing interconnections among the plurality of resistor elements and among the plurality of capacitor elements, respectively, in any given combination by simply modifying the respective interconnection patterns instead of the entire module. With this configuration, a high frequency module of a more compact and lighter type which facilitates design modification is provided at a low cost.

Abstract translation: 高频模块设置有具有互连的电阻器阵列层，其中具有规定电阻值的多个电阻元件形成为阵列，并且其中预先形成用于提供与每个电阻器元件的电连接的互连图案 。 此外，具有互连的电容器阵列层，其中具有规定的电容值的多个电容器元件形成为阵列，并且还预先形成用于提供与每个电容器元件的电连接的互连图案供稍后使用。 通过仅通过简单地修改相应的互连图案而不是整个模块，分别在多个电阻元件之间和多个电容器元件之间分别提供互连来获得期望的电路常数。 利用这种配置，以低成本提供了便于设计修改的更紧凑和更轻型的高频模块。

公开(公告)号：US20020125566A1

公开(公告)日：2002-09-12

申请号：US10087915

申请日：2002-03-05

Inventor： Yoshiyuki Tonami ,  Mitsunori Hatada

IPC: H01L023/34

CPC classification number: H05K3/4061 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/16 ,  H05K1/167 ,  H05K3/048 ,  H05K2201/0317 ,  H05K2203/025 ,  H05K2203/1461 ,  H01L2924/00

Abstract: In the production of a high frequency circuit chip in which a wiring pattern is disposed on a substrate having a through-hole, a connecting electrode of the through-hole is formed by filling electrically conductive paste into a perforation and firing it, and the wiring pattern is formed by a lift-off method. Moreover, at least the surface of the substrate for the wiring pattern to be formed thereon is mirror-polished, and thereafter, the wiring pattern is formed on the mirror-polished surface by the lift-off method.

Abstract translation: 在其中在具有通孔的基板上布置布线图案的高频电路芯片的生产中，通过将导电浆料填充到穿孔中并将其烧结而形成通孔的连接电极，并且布线 图案由剥离法形成。 此外，至少将要形成其上的布线图案的基板的表面进行镜面抛光，然后通过剥离方法在镜面抛光表面上形成布线图案。

公开(公告)号：US06448184B1

公开(公告)日：2002-09-10

申请号：US09187363

申请日：1998-11-06

Applicant: Jerry W. Zimmer ,  Daniel A. Worsham

Inventor： Jerry W. Zimmer ,  Daniel A. Worsham

IPC: H01L21302

CPC classification number: H01L21/32139 ,  H01L23/49877 ,  H01L2924/0002 ,  H05K1/09 ,  H05K3/325 ,  H05K2201/0317 ,  H05K2201/0323 ,  H05K2201/0326 ,  Y10S438/964 ,  H01L2924/00

Abstract: Rough, conductive diamond film regions are formed on a substrate for establishing electrical contact with a surface mount semiconductor package, or the like. The substrate base is heated in a diamond film gas phase deposition reactor. Molecular hydrogen, a carbon-bearing gas and a dopant source are introduced into the reactor at a temperature conducive to producing a conductive polycrystalline diamond film with sharp facets extending from the film. The diamond film is patterned by etching to remove regions where no electrical contact with the surface mount package is desired.

Abstract translation: 粗糙的导电金刚石膜区域形成在用于建立与表面安装半导体封装等的电接触的基板上。 衬底基底在金刚石膜气相沉积反应器中加热。 分子氢，含碳气体和掺杂剂源在有助于生产具有从膜延伸的尖锐面的导电多晶金刚石膜的温度下引入反应器。 通过蚀刻对金刚石膜进行图案化，以去除不需要与表面贴装封装电接触的区域。