公开(公告)号：US20070285884A1

公开(公告)日：2007-12-13

申请号：US11841351

申请日：2007-08-20

Applicant: Teck Lee

Inventor： Teck Lee

IPC: G06F1/18

CPC classification number: H01L23/13 ,  G06F1/18 ,  G06F1/183 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K1/0271 ,  H05K1/0284 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09481 ,  H05K2201/10719 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are formed from a core material of the interposer, such that the interposer may absorb thermally induced stresses and conform to warped or uneven surfaces. Embodiments of electronic device packages including a semiconductor die mounted to and electrically connected to the interposer, as well as methods for forming the electronic device packages, are also disclosed. In one electronic device package, the semiconductor die is electrically connected to the interposer with wire bonds attached to a routing layer of the interposer. In another electronic device package, the semiconductor die is electrically connected to the interposer by bonding the semiconductor die to the flexible solder pad elements of the interposer in a flip-chip configuration. A computer system incorporating an electronic device package with an interposer according to the present invention is also disclosed.

Abstract translation: 公开了用于安装半导体管芯的插入件的各种实施例以及用于形成插入件的方法。 插入器包括由插入器的芯材料形成的柔性焊盘元件，使得插入器可以吸收热诱导的应力并且符合​​翘曲或不平坦的表面。 还公开了包括安装到内插器并且电连接到插入器的半导体管芯的电子器件封装的实施例以及用于形成电子器件封装的方法。 在一个电子器件封装中，半导体管芯通过连接到插入器的布线层上的引线电连接到插入器。 在另一个电子器件封装中，半导体管芯通过以倒装芯片配置将半导体管芯连接到插入器的柔性焊盘元件而电连接到插入器。 还公开了一种结合根据本发明的具有插入器的电子器件封装的计算机系统。

公开(公告)号：US20070211403A1

公开(公告)日：2007-09-13

申请号：US11708970

申请日：2007-02-20

Applicant: Daniel Sievenpiper ,  Joseph Pikulski ,  James Schaffner ,  Tsung-Yuan Hsu

Inventor： Daniel Sievenpiper ,  Joseph Pikulski ,  James Schaffner ,  Tsung-Yuan Hsu

IPC: H01G7/00

CPC classification number: H05K1/162 ,  H01G4/005 ,  H01G4/38 ,  H05K1/144 ,  H05K3/045 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/426 ,  H05K2201/041 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09981 ,  H05K2203/0455

Abstract: A high impedance surface and a method of making same. The surface includes a molded structure having a repeating pattern of holes therein and a repeating pattern of sidewall surfaces, the holes penetrating the structure between first and second major surfaces thereof and the sidewall surfaces joining the first major surface. A metal layer is put on said molded structure, the metal layer being in the holes, covering at least a portion of the second major surface, covering the sidewalls and portions of the first major surface to interconnect the sidewalls with other sidewalls via the metal layer on the second major surface and in the holes.

Abstract translation: 高阻抗表面及其制造方法。 该表面包括具有其中的重复图案的模制结构和侧壁表面的重复图案，该孔贯穿其第一和第二主表面之间的结构以及连接第一主表面的侧壁表面。 金属层放置在所述模制结构上，金属层在孔中，覆盖第二主表面的至少一部分，覆盖第一主表面的侧壁和部分，以通过金属层将侧壁与其它侧壁互连 在第二个主表面和孔中。

公开(公告)号：US20070200554A1

公开(公告)日：2007-08-30

申请号：US11513478

申请日：2006-08-31

Applicant: Tetsuo Yumoto

Inventor： Tetsuo Yumoto

IPC: G01R31/28

CPC classification number: G01R31/28 ,  H05K1/0284 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09236 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09854 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165 ,  Y10T29/49176

Abstract: A molding pin for a metal die is prevented from breaking, solder is surely deposited, and thus, a circuit pitch can be reduced to the limit. On the front plane of a circuit board, prescribed circuit patterns made of a conductive material are formed, and on the rear plane, prescribed circuit patterns are also formed. On the circuit board, a through hole is formed to carry electricity between the circuit patterns on both planes. The inner shape of the through hole is narrow in a direction between the adjacent circuit patterns and wide in a circuit extending direction.

Abstract translation: 防止金属模具的成型销断裂，确实沉积焊料，因此可以将电路间距减小到极限。 在电路板的正面上，形成由导电材料制成的规定的电路图案，在背面也形成规定的电路图形。 在电路板上，形成通孔，以在两个平面上的电路图案之间承载电力。 通孔的内部形状在相邻电路图案之间的方向上窄，并且在电路延伸方向上宽。

公开(公告)号：US20070126115A1

公开(公告)日：2007-06-07

申请号：US11593617

申请日：2006-11-07

Applicant: Manabu Yanagihara ,  Hiroaki Ueno ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

Inventor： Manabu Yanagihara ,  Hiroaki Ueno ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC: H01L23/34

CPC classification number: H05K3/28 ,  H01L21/563 ,  H01L23/3732 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83951 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0209 ,  H05K2201/0179 ,  H05K2201/0323 ,  H05K2201/09045 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A package substrate has a substrate body on which an electronic component is mounted. The substrate body is formed at its top or back surface with a diamond film, a diamond-like carbon film or a carbon film.

Abstract translation: 封装基板具有安装电子部件的基板主体。 基板主体在其顶部或背面形成有金刚石膜，类金刚石碳膜或碳膜。

公开(公告)号：US07197800B2

公开(公告)日：2007-04-03

申请号：US10728506

申请日：2003-12-05

Applicant: Daniel F. Sievenpiper ,  Joseph L. Pikulski ,  James H. Schaffner ,  Tsung-Yuan Hsu

Inventor： Daniel F. Sievenpiper ,  Joseph L. Pikulski ,  James H. Schaffner ,  Tsung-Yuan Hsu

IPC: H01G7/00

CPC classification number: H05K1/162 ,  H01Q15/008 ,  H01Q15/14 ,  H01Q15/141 ,  H05K1/0284 ,  H05K3/045 ,  H05K3/4614 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09672 ,  H05K2201/09981 ,  H05K2203/0455 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49174

Abstract: A high impedance surface and a method of making same. The surface includes a molded structure having a repeating pattern of holes therein and a repeating pattern of sidewall surfaces, the holes penetrating the structure between first and second major surfaces thereof and the sidewall surfaces joining the first major surface. A metal layer is put on said molded structure, the metal layer being in the holes, covering at least a portion of the second major surface, covering the sidewalls and portions of the first major surface to interconnect the sidewalls with other sidewalls via the metal layer on the second major surface and in the holes.

Abstract translation: 高阻抗表面及其制造方法。 该表面包括具有其中的重复图案的模制结构和侧壁表面的重复图案，所述孔贯穿其第一和第二主表面之间的结构以及连接第一主表面的侧壁表面。 金属层放置在所述模制结构上，金属层在孔中，覆盖第二主表面的至少一部分，覆盖第一主表面的侧壁和部分，以通过金属层将侧壁与其它侧壁互连 在第二个主表面和孔中。

公开(公告)号：US07190073B2

公开(公告)日：2007-03-13

申请号：US11158164

申请日：2005-06-20

Applicant: Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee ,  Kyoung-Sei Choi

Inventor： Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee ,  Kyoung-Sei Choi

IPC: H01L23/48

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L23/49811 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H05K3/0032 ,  H05K3/323 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A circuit film having film bumps is provided for a film package. An IC chip is mechanically joined and electrically coupled to the circuit film through the film bumps instead of conventional chip bumps. In a fabrication method, a base film is partially etched by a laser to create an etched area that defines raised portion relatively raised from the etched area. Then a circuit pattern is selectively formed on the base film, partly running over the raised portions. The raised portion and the overlying circuit pattern constitute the film bumps having a height not greater than the height of the circuit film.

Abstract translation: 为薄膜封装提供具有膜凸块的电路薄膜。 IC芯片通过膜凸块机械连接并电耦合到电路膜，而不是传统的芯片凸块。 在制造方法中，通过激光部分地蚀刻基底膜以产生限定从蚀刻区域相对升高的凸起部分的蚀刻区域。 然后，在基膜上选择性地形成电路图案，部分地在凸起部分上运行。 凸起部分和上覆电路图案构成具有不大于电路膜高度的高度的膜凸块。

公开(公告)号：US07183196B2

公开(公告)日：2007-02-27

申请号：US11026971

申请日：2004-12-30

Applicant: Shigetsugu Muramatsu ,  Masato Tanaka ,  Katsumi Yamazaki

Inventor： Shigetsugu Muramatsu ,  Masato Tanaka ,  Katsumi Yamazaki

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/48 ,  H01L21/52 ,  H01L21/40

CPC classification number: H05K3/465 ,  H05K1/115 ,  H05K3/005 ,  H05K3/107 ,  H05K3/421 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2203/0108 ,  H05K2203/0733 ,  H05K2203/1189

Abstract: A multilayer interconnection board is disclosed that allows reliable electrical connection between an interconnection having a large width and a large area and a via provided in a via hole formed by pressing a tool against resin. A projecting portion for electrical connection is formed integrally with the insulating member and in a second interconnection groove having a width and an area greater than those of a first interconnection groove. While a first interconnection is being deposited in the first interconnection groove and a second interconnection is being deposited in the second interconnection groove, the projecting portion is formed in the second interconnection groove and a metal plating film is provided on the projecting portion at the same time, so as to electrically connect the second interconnection with the via.

Abstract translation: 公开了一种多层互连板，其允许具有大宽度和大面积的互连之间的可靠电连接，以及设置在通过将工具压靠树脂而形成的通孔中的通孔。 用于电连接的突出部分与绝缘构件一体地形成在具有大于第一互连槽的宽度和面积的第二互连槽中。 当在第一互连槽中沉积第一互连件并且第二互连件被沉积在第二互连槽中时，突出部分形成在第二互连槽中，同时在突出部分上设置金属镀膜 以便将第二互连电路与通孔电连接。

公开(公告)号：US20070035690A1

公开(公告)日：2007-02-15

申请号：US11161588

申请日：2005-08-09

Applicant: Po-Lung Chen

Inventor： Po-Lung Chen

IPC: G02F1/1345

CPC classification number: H05K3/361 ,  G02F1/13452 ,  H01L24/50 ,  H01L2924/12044 ,  H05K2201/09045 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A display including a display panel, a circuit board and a tape carrier package structure is provided. The circuit board is disposed at the display panel. The tape carrier package structure includes a substrate having an opening, a plurality of leads, a chip, and a blocking bar. The substrate is between the display panel and the circuit board. A plurality of leads, each having an inner lead and outer lead, are disposed around the opening on the substrate. A portion of the outer leads is electrically connected to the display panel, and another portion is electrically connected to the circuit board. The chip has a plurality of contact points, and is disposed at the opening of the substrate. The contact points are electrically connected to the inner leads. Moreover, the blocking bar is disposed on the substrate between the chip and the display panel.

Abstract translation: 提供了包括显示面板，电路板和带状载体封装结构的显示器。 电路板设置在显示面板上。 带状载体封装结构包括具有开口的基板，多个引线，芯片和阻挡条。 基板位于显示面板和电路板之间。 每个具有内引线和外引线的引线设置在基板上的开口周围。 外引线的一部分电连接到显示面板，另一部分电连接到电路板。 芯片具有多个接触点，并且设置在基板的开口处。 接触点电连接到内引线。 此外，阻挡杆设置在芯片和显示面板之间的基板上。

公开(公告)号：US07159311B2

公开(公告)日：2007-01-09

申请号：US10365874

申请日：2003-02-13

Applicant: James M. Wark ,  Salman Akram

Inventor： James M. Wark ,  Salman Akram

IPC: H01R9/00 ,  H05K3/00

CPC classification number: H01R12/57 ,  G01R1/0408 ,  G01R1/0466 ,  H01L2924/0002 ,  H01R43/205 ,  H05K1/119 ,  H05K3/325 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  H05K2201/09472 ,  H05K2201/10689 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49179 ,  Y10T29/49222 ,  Y10T29/49453 ,  H01L2924/00

Abstract: A method of making an interposer having an array of contact structures for making temporary electrical contact with the leads of a chip package. The contact structures may make contact with the leads substantially as close as desired to the body of the chip package. Moreover, the contact structures can be adapted for making contact with leads having a very fine pitch. In a first embodiment, the contact structures include raised members formed over a body of the interposer. A conductive layer is formed over each of the raised members to provide a contact surface for engaging the leads of the chip package. In another embodiment, the raised members are replaced with depressions formed into the interposer. A conductive layer is formed on an inside surface of each depression to provide a contact surface for engaging the leads of the chip package. Moreover, any combination of raised members and depressions may be used.

Abstract translation: 一种制造具有用于与芯片封装的引线暂时电接触的接触结构阵列的插入件的方法。 接触结构可以与引线基本上接近于芯片封装体的所需位置。 此外，接触结构可以适于与具有非常细的间距的引线接触。 在第一实施例中，接触结构包括形成在插入件的主体上的凸起部件。 在每个凸起构件上形成导电层，以提供用于接合芯片封装引线的接触表面。 在另一个实施例中，凸起构件被形成在插入件中的凹陷所代替。 在每个凹陷的内表面上形成导电层，以提供用于接合芯片封装的引线的接触表面。 此外，可以使用凸起构件和凹陷的任何组合。

公开(公告)号：US20060283627A1

公开(公告)日：2006-12-21

申请号：US11302165

申请日：2005-12-14

Applicant: Ying-Chou Chen ,  Ying-Te Ou ,  Chiu-Wen Lee

Inventor： Ying-Chou Chen ,  Ying-Te Ou ,  Chiu-Wen Lee

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/183 ,  H05K3/284 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/09045 ,  H05K2201/10636 ,  H05K2201/2036 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: The present invention is related to a substrate structure and a method for fabricating the substrate, and more particularly to a substrate structure of integrated embedded passive components and a method for fabricating the substrate. In the present invention, the openings are formed on the substrate by removing part of external circuit layer and part of dielectric layer. Then, the embedded components are disposed in these openings. Therefore, the shift and short circuit of the passive components caused by the flow and gather of the solder paste in reflow or other high-temperature processes can be improved.

Abstract translation: 本发明涉及衬底结构和用于制造衬底的方法，更具体地涉及集成嵌入式无源组件的衬底结构和制造衬底的方法。 在本发明中，通过去除外部电路层的一部分和电介质层的一部分，在基板上形成开口。 然后，嵌入式部件设置在这些开口部中。 因此，可以提高由回流焊或其他高温工艺中的焊膏的流动和聚集引起的无源部件的偏移和短路。