公开(公告)号：US20230189437A1

公开(公告)日：2023-06-15

申请号：US18165964

申请日：2023-02-08

Applicant: ORPYX MEDICAL TECHNOLOGIES INC.

Inventor： DAVID ALLAN VIBERG ,  TRAVIS MICHAEL STEVENS ,  KRAIG ELBERT NIELSEN ,  MICHAEL TODD PURDY

IPC: H05K1/02 ,  G01K1/02 ,  G01K7/00 ,  G01L1/14

CPC classification number: H05K1/0296 ,  G01K1/026 ,  G01K7/00 ,  G01L1/146 ,  H05K1/0272 ,  H05K1/0281 ,  H05K2201/09227 ,  H05K2201/0979 ,  H05K2201/10151

Abstract: A flexible circuit package. The circuit package includes a termination point on a flexible base substrate. The termination point is connected with an interface by conductive material on the base substrate. The conductive material extends across the surface area of the base substrate in multiple individual connections, which are in communication with each other and separated by voids in the conductive material for mitigating communication failure between the termination point and the interface during or following flexion, stretching, compression or other deformation of the base substrate and the circuit package. The termination point may include an input module such as a sensor, switch or other input. The termination point may include an output module such as a light, vibrator or other output. The interface may include an output interface for receiving data or an input interface for sending a command or other signal.

公开(公告)号：US20230163058A1

公开(公告)日：2023-05-25

申请号：US17580664

申请日：2022-01-21

Applicant: VIA Technologies, Inc.

Inventor： Nai-Shung Chang ,  Yun-Han Chen ,  Tsai-Sheng Chen ,  Chang-Li Tan ,  Sheng-Bang Ou Yang

IPC: H01L23/498 ,  H05K1/11 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H05K1/112 ,  H05K1/0245 ,  H05K2201/09227 ,  H05K2201/094

Abstract: A contact arrangement includes a plurality of contact groups. At least one of the contact groups includes a plurality of shared contacts, a plurality of dedicated contacts, and a plurality of ground contacts. The shared contacts in a first mode or a second mode transmit signals corresponding to the first mode or the second mode. The dedicated contacts transmit the signals corresponding to the first mode and do not transmit the signals corresponding to the second mode. The ground contacts surround the shared contacts and the dedicated contacts.

公开(公告)号：US11657862B2

公开(公告)日：2023-05-23

申请号：US16361837

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Rogelio Alfonso Moreyra Gonzalez ,  Jose Angel Ramos Martinez ,  James McCall

IPC: G11C5/06 ,  G11C7/22 ,  H05K1/18 ,  H05K1/02 ,  G11C5/04

CPC classification number: G11C7/222 ,  H05K1/0298 ,  H05K1/181 ,  G11C5/04 ,  H05K2201/09227 ,  H05K2201/09327 ,  H05K2201/10159

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to facilitating increased clock speeds on a substrate by lowering the impedance of traces that provide clock signals to components such as DRAM. For example, embodiments may include a substrate with a first layer and a second layer parallel to the first layer with a first trace coupled with the first layer in a routing configuration and a second trace coupled with the second layer in the routing configuration, where the routing configuration of the first trace and the second trace substantially overlap each other with respect to an axis perpendicular to the first layer and the second layer, and where the first trace and the second trace are electrically coupled by a first and a second electrical coupling perpendicular to the first layer and the second layer.

公开(公告)号：US20190124766A1

公开(公告)日：2019-04-25

申请号：US16166392

申请日：2018-10-22

Applicant: IBIDEN CO., LTD.

Inventor： Takema ADACHI ,  Toshihide Makino ,  Hidetoshi Noguchi

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/16

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/16 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09727 ,  H05K2201/09827 ,  H05K2203/107 ,  H05K2203/1572

Abstract: A printed wiring board includes: a core substrate having a core layer and first and second conductor layers; a first build-up layer including a first insulating layer, an inner first conductor layer, an outermost first insulating layer, and an outermost first conductor layer; and a second build-up layer including a second insulating layer, an inner second conductor layer, an outermost second insulating layer, and an outermost second conductor layer. Each conductor layer includes metal foil, seed layer, and electrolytic plating film, t1/T1, t2/T2, u1/U1 and u2/U2 are smaller than 1, and s1/S1 and s2/S2 are larger than 1, where t1, t2, u1, u2, s1 and s2 are electrolytic plating film thicknesses of the first and second and outermost and inner first and second conductor layers, T1, T2, U1 , U2, S1 and S2 are metal foil thicknesses of the first and second and outermost and inner first and second conductor layers.

公开(公告)号：US20180359862A1

公开(公告)日：2018-12-13

申请号：US16002112

申请日：2018-06-07

Applicant: Fracatal Antenna Systems, Inc.

Inventor： Nathan Cohen

IPC: H05K3/28 ,  H05K3/12 ,  H05K1/02

CPC classification number: H05K3/282 ,  H05K1/0245 ,  H05K1/0256 ,  H05K1/0296 ,  H05K1/0298 ,  H05K3/1258 ,  H05K2201/0769 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09281

Abstract: Methods are disclosed which discourage formation of destructive corrosion on or about circuit traces of printed circuit boards, and/or mitigate electronic circuit degradation and or destruction through corrosion of the circuit traces, whereby said corrosion produces changing characteristics of the circuit, and/or shorting to other adjacent circuit traces. Aspects and embodiments of the present disclosure include or provide for forming at least a portion of a circuit trace or traces with fractal and/or self-complementary geometries, or self complementary geometry alone.

公开(公告)号：US20180315735A1

公开(公告)日：2018-11-01

申请号：US15499557

申请日：2017-04-27

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba

IPC: H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/49894 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H05K1/0243 ,  H05K1/185 ,  H05K3/4694 ,  H05K2201/09227 ,  H05K2201/10015 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10674

Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide improved signal transmission of 1-2 GHz up to 20-60 GHz bandwidth for each 15 mm length, for example. The embedded organic interposers are not limited to use with memory modules.

公开(公告)号：US20180295719A1

公开(公告)日：2018-10-11

申请号：US15570879

申请日：2015-06-29

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Charles Nathan Logan ,  Adrian Rothenbuhler ,  Christine m. Wells

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K3/40

CPC classification number: H05K1/0275 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/111 ,  H05K1/112 ,  H05K3/4007 ,  H05K3/4038 ,  H05K2201/09227 ,  H05K2201/094 ,  H05K2201/09409 ,  H05K2201/09781

Abstract: In one implementation, a printed circuit board (PCB) includes a plurality of pads that form a pad pattern on the PCB. In that implementation, the plurality of pads include a group of load pads, a dummy pad, and a false pad. The group of load pads act as contact points to establish an electrical path between a first circuitry and a second circuitry. The dummy pad is coupled to a via that floats electrically and the false pad is coupled to a third circuitry.

公开(公告)号：US20180288871A1

公开(公告)日：2018-10-04

申请号：US15938403

申请日：2018-03-28

Applicant: NIDEC SANKYO CORPORATION

Inventor： Masaya FUJIMOTO ,  Junro TAKEUCHI

IPC: H05K1/02 ,  G06K7/08

CPC classification number: H05K1/0275 ,  G06K7/087 ,  H05K1/028 ,  H05K1/118 ,  H05K2201/09027 ,  H05K2201/09227

Abstract: A flexible printed circuit board may include a data signal circuit layer on which a data signal circuit is formed; and a destruction detection circuit layer on which a destruction detection circuit, structured to detect at least one of a break and a short-circuit of the destruction detection circuit layer, is formed, the destruction detection circuit layer overlapping the data signal circuit layer. The destruction detection circuit may be structured to carry destruction detection signals which are squarewave-shaped digital signals. The data signal circuit layer may include a first data signal circuit layer on which the data signal circuit is formed, the data signal circuit including linear-shaped first pattern wirings arranged parallel to one another. The destruction detection circuit may include a first destruction detection circuit layer including second pattern wirings formed by a linear portions orthogonally crossing the first pattern wirings and arcuate portions.

公开(公告)号：US10079202B2

公开(公告)日：2018-09-18

申请号：US14721263

申请日：2015-05-26

Applicant: Thomas P Warwick

Inventor： Thomas P Warwick

IPC: H05K1/11 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/552 ,  H05K1/02

CPC classification number: H01L23/5225 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15313 ,  H01L2924/3011 ,  H05K1/0222 ,  H05K1/0243 ,  H05K1/113 ,  H05K1/116 ,  H05K2201/0723 ,  H05K2201/09227 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K2201/10674 ,  H05K2203/0207

Abstract: Due to size and cost, it becomes advantageous for integrated circuit (IC) manufacturers to use “single-ended” (one signal path per unique information path) high speed signals electrical contact pins (pins transmitting digital information that connect the integrated circuit to a printed circuit board) with a minimum number of surrounding powers and grounds. This lower cost method, however, creates electrical interference and coupling issues known as crosstalk between two adjacent signal paths in the via structure required to electrically connect the integrated circuit to the signal paths in the printed circuit board. Such crosstalk, in turn, increases jitter, degrades timing, and ultimately reduces the maximum operating speed of the circuit (performance). This disclosure presents a structure using micro-plating, micro-drilling and micro-machining methods that isolates adjacent signals by placing a metal barrier that shunts coupling currents to ground. The micro-drilling methods also reduce the length of adjacent signal paths in a specific signal routing and controlled depth drilling sequence.

公开(公告)号：US20180249576A1

公开(公告)日：2018-08-30

申请号：US15547851

申请日：2016-01-28

Applicant: FUJIKURA LTD.

Inventor： Shingo Ogura

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0283 ,  H01B5/14 ,  H05K1/02 ,  H05K1/0393 ,  H05K1/118 ,  H05K3/1283 ,  H05K3/24 ,  H05K3/28 ,  H05K3/285 ,  H05K3/287 ,  H05K2201/0133 ,  H05K2201/0162 ,  H05K2201/0187 ,  H05K2201/09227

Abstract: A stretchable wiring board includes: a stretchable base; at least one stretchable wiring provided on the stretchable base; and a poorly stretchable member provided so as to overlap at least part of the stretchable wiring in a thickness direction looking at the stretchable base in planar view. The poorly stretchable member suppresses change in a resistance value of the stretchable wiring associated with stretching deformation of the stretchable base. As a result, stable operability can be secured without affecting an operating voltage of an electronic component.