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    WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE
    1.
    发明申请
    WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE 有权

    公开(公告)号：US20220338347A1

    公开(公告)日：2022-10-20

    申请号：US17708486

    申请日：2022-03-30

    Applicant: IBIDEN CO., LTD.

    Inventor： Takema ADACHI ,  Daisuke MINOURA

    IPC: H05K1/11 ,  H05K3/38

    Abstract: A wiring substrate includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, a connection conductor penetrating through the insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer and adhering the first conductor layer and the insulating layer. The first conductor layer includes a conductor pad in contact with the connection conductor such that the conductor pad has a surface having a first region and a second region on second conductor layer side and that surface roughness of the first region is different from surface roughness of the second region, and the conductor pad of the first conductor layer is formed such that the first region is covered by the coating film and that the second region is covered by the connection conductor.

    METHOD FOR MANUFACTURING WIRING BOARD WITH CONDUCTIVE POST
    2.
    发明申请
    METHOD FOR MANUFACTURING WIRING BOARD WITH CONDUCTIVE POST 审中-公开
    制造导线板的方法

    公开(公告)号：US20150271929A1

    公开(公告)日：2015-09-24

    申请号：US14663559

    申请日：2015-03-20

    Applicant: IBIDEN CO., LTD.

    Inventor： Kota NODA ,  Takema ADACHI ,  Wataru NAKAMURA

    IPC: H05K3/42 ,  C25D5/02 ,  C25D5/34 ,  C25D7/12 ,  C25D5/48

    CPC classification number: C25D5/022 ,  C23C18/1605 ,  C23C18/1653 ,  C23C18/38 ,  C25D5/10 ,  C25D5/12 ,  C25D7/00 ,  C25D7/123 ,  H05K3/108 ,  H05K3/244 ,  H05K3/4007 ,  H05K3/4644

    Abstract: A method for manufacturing a wiring board having conductive posts includes preparing a wiring board including electronic circuit and a solder resist layer covering the electronic circuit and having first openings and second openings surrounding the first openings such that the first openings are exposing pad portions of the electronic circuit and that the second openings are exposing post connecting portions of the electronic circuit surrounding the pad portions, applying surface treatment to the pad portions, forming a plating resist layer on the wiring board after the surface treatment of the pad portions such that the plating resist layer has resist openings exposing the post connecting portions, applying electrolytic plating on the post connecting portions such that conductive posts rising from the post connecting portions are formed in the resist openings, and removing the plating resist layer from the wiring board after forming the conductive posts in the resist openings.

    Abstract translation: 一种制造具有导电柱的布线板的方法，包括制备包括电子电路的布线板和覆盖电子电路的阻焊层，并且具有围绕第一开口的第一开口和第二开口，使得第一开口暴露电子部件的焊盘部分 并且第二开口暴露围绕焊盘部分的电子电路的连接部分，对焊盘部分进行表面处理，在焊盘部分的表面处理之后在布线板上形成电镀抗蚀剂层，使得电镀抗蚀剂 层具有露出柱连接部分的抗蚀剂开口，在柱连接部分上施加电镀，使得在抗蚀剂开口中形成从柱连接部分上升的导电柱，并且在形成导电柱之后从布线板去除电镀抗蚀剂层 在抗蚀剂开口中。

    WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE
    3.
    发明申请
    WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE 有权

    公开(公告)号：US20220248533A1

    公开(公告)日：2022-08-04

    申请号：US17588457

    申请日：2022-01-31

    Applicant: IBIDEN CO., LTD.

    Inventor： Takema ADACHI ,  Daisuke MINOURA

    IPC: H05K1/11 ,  H05K3/26 ,  H05K3/38 ,  H05K3/42

    Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor penetrating through the second insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer such that the coating film is adhering the first conductor layer and the second insulating layer. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is in contact with the connection conductor and the wiring pattern is covered by the coating film, the conductor pad of the first conductor layer has a surface facing the second insulating layer and having a first surface roughness higher than a surface roughness of a surface of the wiring pattern, and the coating film has opening such that the opening is exposing the conductor pad entirely.

    PRINTED WIRING BOARD
    5.
    发明申请
    PRINTED WIRING BOARD 有权
    印刷线路板

    公开(公告)号：US20130240258A1

    公开(公告)日：2013-09-19

    申请号：US13836123

    申请日：2013-03-15

    Applicant: IBIDEN CO., LTD.

    Inventor： Naoto ISHIDA ,  Takema ADACHI

    IPC: H05K1/03

    CPC classification number: H05K1/0306 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/185 ,  H05K3/4673 ,  H05K2201/0209 ,  H05K2201/068

    Abstract: A printed wiring board includes a core substrate including an insulative substrate, a first conductive layer formed on first surface of the insulative substrate, and a second conductive layer formed on second surface of the insulative substrate, a first buildup laminated on first surface of the core and including an interlayer insulation layer, a conductive layer formed on the insulation layer, and a via conductor penetrating through the insulation layer and connected to the conductive layer, and a second buildup laminated on second surface of the core and including an interlayer insulation layer, a conductive layer formed on the interlayer insulation layer, and a via conductor penetrating through the insulation layer and connected to the conductive layer. The insulation layer of the first buildup has thermal expansion coefficient set higher than thermal expansion coefficient of the insulation layer of the second buildup.

    Abstract translation: 印刷电路板包括具有绝缘基板的芯基板，形成在绝缘基板的第一面上的第一导电层和形成在绝缘基板的第二面上的第二导电层，层叠在芯的第一面上的第一积层 并且包括层间绝缘层，形成在所述绝缘层上的导电层和穿过所述绝缘层并连接到所述导电层的通孔导体，以及层叠在所述芯的第二表面上并包括层间绝缘层的第二堆积层， 形成在层间绝缘层上的导电层和穿过绝缘层并连接到导电层的通孔导体。 第一次堆积的绝缘层的热膨胀系数设定为高于第二次堆积的绝缘层的热膨胀系数。

    PRINTED WIRING BOARD
    6.
    发明申请
    PRINTED WIRING BOARD 有权
    印刷线路板

    公开(公告)号：US20130221518A1

    公开(公告)日：2013-08-29

    申请号：US13690570

    申请日：2012-11-30

    Applicant: IBIDEN CO., LTD.

    Inventor： Naoto ISHIDA ,  Takema ADACHI

    IPC: H05K1/02 ,  H01L23/498

    CPC classification number: H01L23/49544 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/0298 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/068

    Abstract: A printed wiring board includes a core substrate, a first buildup layer laminated on a first surface of the core substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on a second surface of the core substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost conductive layer of the first buildup layer includes pads positioned to mount a semiconductor device on a surface of the first buildup layer, and the outermost interlayer resin insulation layer of the first buildup layer has a thermal expansion coefficient which is set lower than a thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer.

    Abstract translation: 印刷电路板包括芯基板，层叠在芯基板的第一表面上并且包括最外层间树脂绝缘层的第一累积层和形成在第一堆积层的最外层间树脂绝缘层上的最外导电层，以及 层叠在所述芯基板的第二表面上并且包括最外层间树脂绝缘层和形成在所述第二堆积层的最外层间树脂绝缘层上的最外导体层的第二堆积层。 第一累积层的最外面的导电层包括定位成将半导体器件安装在第一堆积层的表面上的焊盘，第一堆积层的最外层间树脂绝缘层的热膨胀系数设定为低于热 第二堆积层的最外层间树脂绝缘层的膨胀系数。

    PRINTED WIRING BOARD
    7.
    发明申请
    PRINTED WIRING BOARD 审中-公开

    公开(公告)号：US20190124768A1

    公开(公告)日：2019-04-25

    申请号：US16167850

    申请日：2018-10-23

    Applicant: IBIDEN CO., LTD.

    Inventor： Takema ADACHI ,  Toshihide MAKINO ,  Hidetoshi NOGUCHI

    IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46 ,  H05K3/42

    Abstract: A printed wiring board includes a core substrate and first and second build-up layers. The substrate includes a core layer, through-hole conductors formed in through holes such that each through hole has first opening tapering from first toward second surface of the core layer, and second opening tapering from second toward first surface of the core layer, and first and second through-hole lands directly connected to the through-hole conductors. Each build-up layer includes an insulating layer, via conductors, via lands, an outermost insulating layer, an outermost conductor layer, and outermost via conductors. Each of the through-hole lands, via lands and outermost conductor layers includes a metal foil, a seed layer and an electrolytic plating film. The foils have mat surfaces such that the mat surfaces of the via lands has ten-point average roughness smaller than ten-point average roughness of the mat surfaces of the through-hole lands and outermost conductor layers.

    PRINTED WIRING BOARD
    8.
    发明申请
    PRINTED WIRING BOARD 审中-公开

    公开(公告)号：US20190124766A1

    公开(公告)日：2019-04-25

    申请号：US16166392

    申请日：2018-10-22

    Applicant: IBIDEN CO., LTD.

    Inventor： Takema ADACHI ,  Toshihide Makino ,  Hidetoshi Noguchi

    IPC: H05K1/11 ,  H05K1/02 ,  H05K1/16

    CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/16 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09727 ,  H05K2201/09827 ,  H05K2203/107 ,  H05K2203/1572

    Abstract: A printed wiring board includes: a core substrate having a core layer and first and second conductor layers; a first build-up layer including a first insulating layer, an inner first conductor layer, an outermost first insulating layer, and an outermost first conductor layer; and a second build-up layer including a second insulating layer, an inner second conductor layer, an outermost second insulating layer, and an outermost second conductor layer. Each conductor layer includes metal foil, seed layer, and electrolytic plating film, t1/T1, t2/T2, u1/U1 and u2/U2 are smaller than 1, and s1/S1 and s2/S2 are larger than 1, where t1, t2, u1, u2, s1 and s2 are electrolytic plating film thicknesses of the first and second and outermost and inner first and second conductor layers, T1, T2, U1 , U2, S1 and S2 are metal foil thicknesses of the first and second and outermost and inner first and second conductor layers.

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