公开(公告)号：US20180242456A1

公开(公告)日：2018-08-23

申请号：US15748100

申请日：2016-08-10

Applicant: Schweizer Electronic AG

Inventor： Thomas GOTTWALD ,  Christian RÖSSLE

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/02 ,  H05K1/11 ,  H01Q1/38

CPC classification number: H05K1/186 ,  H01Q1/38 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/115 ,  H05K1/181 ,  H05K1/185 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/015 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09936 ,  H05K2201/10098 ,  H05K2201/10378 ,  H05K2203/0285 ,  H05K2203/063 ,  H05K2203/166

Abstract: Method for producing a conductor structural element with a layer sequence having an internal layer substrate, including the steps: providing a rigid carrier having an underside and a top side; defining a cut-out section on the rigid carrier; applying at least one electrically insulating layer with a recess in such a way that the cut-out section is exposed; placing an internal layer substrate above the cut-out section with formation of a cavity between the rigid carrier and the internal layer substrate; aligning and fixing the internal layer substrate relative to the rigid carrier; laminating the layer construction prepared in this manner such that resin material of the at least one electrically insulating layer liquefies and encloses the internal layer substrate with the cavity being left free; producing a cut-out by cutting the cut-out section out of the rigid carrier from the outer underside of the rigid carrier.

公开(公告)号：US20180199427A1

公开(公告)日：2018-07-12

申请号：US15859784

申请日：2018-01-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kunihiro MIYAHARA

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0218 ,  H01G4/20 ,  H03H7/0153 ,  H05K1/0224 ,  H05K1/0269 ,  H05K1/115 ,  H05K9/00 ,  H05K9/0049 ,  H05K2201/0195 ,  H05K2201/0715 ,  H05K2201/09936

Abstract: An electronic component includes dielectric layers laminated along a lamination direction and shield electrodes. The dielectric layers include first and second dielectric layers. The side surfaces of the first dielectric layer are not covered with the shield electrodes. The side surfaces of the second dielectric layer are covered with the shield electrodes. The dielectric constant of the first dielectric layer is lower than the second dielectric constant of the dielectric layer.

公开(公告)号：US09857687B2

公开(公告)日：2018-01-02

申请号：US14770979

申请日：2014-02-26

Applicant: TOKAI SHINEI ELECTRONICS INDUSTRY CO., LTD ,  Tadayoshi Saito ,  YAMATOYA & CO., LTD

Inventor： Kazunori Tsuge ,  Yoshihito Tanaka ,  Koji Akiyama ,  Kiyoshi Tanaka ,  Kazuyoshi Nishio ,  Takehiro Kato ,  Masaru Murakami ,  Tadayoshi Saito ,  Hirotoshi Yoshimura ,  Akira Inoue ,  Iwao Numakura ,  Noriaki Tsukada

IPC: G03F7/004 ,  G03F7/09 ,  G03C1/76 ,  G03C1/95 ,  G03F7/20 ,  G03F7/11 ,  H01L23/498 ,  H05K1/02 ,  H05K3/28 ,  G03F1/50 ,  G03F7/32 ,  G03F7/40 ,  H05K3/34

CPC classification number: G03F7/2002 ,  G03C1/76 ,  G03C1/95 ,  G03F1/50 ,  G03F7/0012 ,  G03F7/004 ,  G03F7/038 ,  G03F7/09 ,  G03F7/11 ,  G03F7/2016 ,  G03F7/2022 ,  G03F7/203 ,  G03F7/32 ,  G03F7/40 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0269 ,  H05K3/287 ,  H05K3/341 ,  H05K2201/099 ,  H05K2201/09936 ,  H05K2203/056 ,  H05K2203/0571 ,  H01L2924/00

Abstract: A method of manufacturing a substrate includes applying solder resist ink containing a mixing resin of epoxy-based resin and acrylic-based resin on at least one surface of a substrate body to form a solder resist layer, and irradiating a predetermined portion of the solder resist layer with ultraviolet rays and controlling an amount of irradiation of the ultraviolet rays irradiated to the predetermined of the solder resist layer to form the predetermined portion in transmissivity that transmits light.

公开(公告)号：US20170257945A1

公开(公告)日：2017-09-07

申请号：US15450813

申请日：2017-03-06

Applicant: Infineon Technologies AG

Inventor： Alexander Roth

IPC: H05K1/03 ,  H05K3/46 ,  H05K3/06 ,  H05K1/02

CPC classification number: H05K1/0306 ,  H01L23/12 ,  H01L23/544 ,  H01L2223/54413 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H05K1/0269 ,  H05K1/0284 ,  H05K3/06 ,  H05K3/4644 ,  H05K2201/09145 ,  H05K2201/0929 ,  H05K2201/09936 ,  H05K2203/107

Abstract: A substrate includes a ceramic layer, a metal layer fixed in a planar manner on a surface side of the ceramic layer and a cutout arranged in an edge region of the metal layer. The cutout in the edge region codes information. A multiple substrate having a plurality of these substrates is also provided, as is a method for producing the substrate.

公开(公告)号：US20160105953A1

公开(公告)日：2016-04-14

申请号：US14971688

申请日：2015-12-16

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Nikolai HASLEBNER ,  Markus LEITGEB ,  Michael GOESSLER ,  Mike MORIANZ

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/14 ,  H05K1/11

CPC classification number: H05K1/0266 ,  H01L2224/2518 ,  H05K1/0269 ,  H05K1/028 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/115 ,  H05K1/14 ,  H05K1/18 ,  H05K1/182 ,  H05K1/189 ,  H05K3/36 ,  H05K3/4638 ,  H05K3/4688 ,  H05K2201/0355 ,  H05K2201/058 ,  H05K2201/09918 ,  H05K2201/09936 ,  H05K2203/166 ,  Y10T29/49126

Abstract: For a method for producing a circuit board consisting of a plurality of circuit board areas, wherein the individual circuit board areas comprise at least one layer made of an in insulating base material and a conducting pattern located on or in, the base material, the following is provided: a substrate material, at least one registration mark formed in the substrate material, a first circuit board area arranged on the substrate material, at least one additional circuit board area, which substantially adjoins the first circuit board area or at least partially overlaps the first circuit board, the additional circuit board areas being oriented relative to the registration mark, and a plurality of connections of the conducting patterns of the first circuit board area and of the at least one additional circuit board area. Thus improved registration and orientation can be achieved when circuit board areas are coupled.

Abstract translation: 对于用于制造由多个电路板区域组成的电路板的方法，其中各个电路板区域包括至少一层由绝缘基材制成的层和位于基材上或其中的导电图案，下列 提供：衬底材料，形成在衬底材料中的至少一个对准标记，布置在衬底材料上的第一电路板区域，至少一个额外的电路板区域，其基本上邻接第一电路板区域或至少部分重叠 所述第一电路板，所述附加电路板区域相对于所述对准标记定向，以及所述第一电路板区域和所述至少一个附加电路板区域的导电图案的多个连接。 因此，当电路板区域耦合时，可以实现改进的配准和取向。

公开(公告)号：US09282633B2

公开(公告)日：2016-03-08

申请号：US13519374

申请日：2012-06-11

Applicant: Hua Zheng ,  Cheng-hung Chen

Inventor： Hua Zheng ,  Cheng-hung Chen

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0269 ,  H05K1/0289 ,  H05K2201/09281 ,  H05K2201/09936

Abstract: The present invention provides a routing structure and display panel. The routing structure includes a plurality of routing, disposed separately. Each routing corresponds to a symbol, and the symbol is disposed on the routing to act as a part of the routing to conduct electricity. In this manner, the routing structure and display panel of the present invention allow expansion of routing width, effectively reduce RC constant and energy-consumption, and improve yield rate.

Abstract translation: 本发明提供一种路由结构和显示面板。 路由结构包括多个路由，分开设置。 每个路由对应于符号，并且该符号被布置在路由上以充当路由的一部分以进行电力。 以这种方式，本发明的路由结构和显示面板允许扩展路由宽度，有效降低RC常数和能量消耗，并提高成品率。

公开(公告)号：US09253877B2

公开(公告)日：2016-02-02

申请号：US14633342

申请日：2015-02-27

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Takashi Sato ,  Ruofan Tang

IPC: H01L23/544 ,  H01L23/12 ,  H05K1/02 ,  H01L23/498 ,  H05K1/11

CPC classification number: H05K1/0269 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/115 ,  H05K3/4682 ,  H05K2201/09409 ,  H05K2201/09609 ,  H05K2201/09781 ,  H05K2201/09936 ,  H01L2924/00

Abstract: A wiring substrate includes wiring layers and insulation layers alternately stacked. Via holes are formed in the insulation layers. First via wirings are formed in the via holes to electrically connect the wiring layers to one another. Through holes extend through a lowermost one of the insulation layers in a thickness direction. The lowermost insulation layer covers a lowermost one of the wiring layers. Second via wirings are formed in the through holes to define an identification mark that is identifiable as a specific shape including a character, a symbol, or a combination thereof. A lower surface of each of the second via wirings is exposed from a lower surface of the lowermost insulation layer and is flush with a lower surface of the lowermost wiring layer.

Abstract translation: 布线基板包括交替堆叠的布线层和绝缘层。 在绝缘层中形成通孔。 首先通过布线形成通孔，以将布线层彼此电连接。 通孔在厚度方向上延伸穿过绝缘层中的最下面一个。 最下面的绝缘层覆盖最下面的一个布线层。 第二通孔布线形成在通孔中以形成可识别为包括字符，符号或其组合的特定形状的识别标记。 每个第二通孔布线的下表面从最下层绝缘层的下表面露出，并且与最下布线层的下表面齐平。

公开(公告)号：US09249959B2

公开(公告)日：2016-02-02

申请号：US14245749

申请日：2014-04-04

Applicant: Novalia Ltd

Inventor： Kate Stone

IPC: H05K7/10 ,  F21V21/14 ,  H05K1/03 ,  H05K3/32 ,  H05K3/36 ,  H05K1/02 ,  H05K1/11 ,  H05K3/12

CPC classification number: F21V21/14 ,  H05K1/0266 ,  H05K1/028 ,  H05K1/038 ,  H05K1/0393 ,  H05K1/113 ,  H05K3/12 ,  H05K3/32 ,  H05K3/321 ,  H05K3/361 ,  H05K2201/09063 ,  H05K2201/09072 ,  H05K2201/091 ,  H05K2201/09936 ,  H05K2201/10674 ,  H05K2203/1545 ,  Y10T29/4913 ,  Y10T29/5313 ,  Y10T428/24273

Abstract: A method of fabricating packaging for a product comprises forming a plurality of conductive tracks on a sheet of material and forming a physical barrier, such as a hole, for impeding fluid flow between adjacent conductive tracks. The method may further comprise depositing first and second regions conductive fluid onto adjacent first and second conductive tracks either side of the physical barrier and mounting an electronic device having first and second terminals such that the electronic device forms a bridge over the physical barrier and the first ands second terminals contact the first and second conductive adjacent tracks.

Abstract translation: 一种制造产品包装的方法包括在一片材料上形成多个导电轨迹并形成物理屏障，例如孔，用于阻止相邻导电轨道之间的流体流动。 该方法还可以包括将第一和第二区域导电流体沉积到物理屏障两侧的相邻第一和第二导电轨道上，并且安装具有第一和第二端子的电子设备，使得电子设备在物理屏障上形成桥， 并且第二端子接触第一和第二导电相邻轨道。

公开(公告)号：US20140307382A1

公开(公告)日：2014-10-16

申请号：US14307288

申请日：2014-06-17

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takakatsu MORIAI ,  Toyokazu EGUCHI ,  Atsushi KANEKO ,  Atsushi OKADA

IPC: G06F1/18

CPC classification number: G06F1/185 ,  G06F1/20 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/02 ,  H05K1/0298 ,  H05K3/0052 ,  H05K7/20472 ,  H05K2201/09145 ,  H05K2201/09936 ,  H05K2201/10409 ,  H01L2924/00

Abstract: According to one embodiment, coupling capacitance in a state in which a first heat radiation member is arranged between parallel flat plates of a first capacitor formed by a surface of a housing opposed to one surface of a printed circuit board and the printed circuit board is smaller than coupling capacitance in a state in which an integrally formed object having a relative dielectric constant of 5.8 is arranged between the first capacitor to cover a first radiating region containing the controller and the first nonvolatile semiconductor memories.

Abstract translation: 根据一个实施例，在第一散热构件布置在由与印刷电路板的一个表面相对的壳体的表面形成的第一电容器的平行平板和印刷电路板之间的状态下的耦合电容较小 在第一电容器之间布置有相对介电常数为5.8的整体形成的物体的状态下的耦合电容，以覆盖包含控制器的第一辐射区域和第一非易失性半导体存储器。

公开(公告)号：US20140175705A1

公开(公告)日：2014-06-26

申请号：US14136872

申请日：2013-12-20

Applicant: NGK Spark Plug Co., Ltd.

Inventor： Yousuke MORITA

IPC: B29C59/16

CPC classification number: H05K1/0269 ,  B23K26/048 ,  B23K26/082 ,  B23K26/083 ,  B23K26/361 ,  H05K3/0032 ,  H05K3/28 ,  H05K2201/09936 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/1476

Abstract: A method for manufacturing a substrate includes manufacturing a substrate with an identifying mark having a plurality of elements, the substrate having a laminated construction including a plurality of resin insulating layers. The method includes the steps of: forming a first element of the identifying mark by irradiating the substrate with a laser to create a first plurality of projections in parallel at equal intervals; and forming another element of the identifying mark by irradiating the substrate with a laser to create a second plurality of projections in parallel at equal intervals that do not overlap the first plurality of projections.

Abstract translation: 一种基板的制造方法，其特征在于，制造具有多个元件的识别标记的基板，所述基板具有包含多个树脂绝缘层的叠层结构。 该方法包括以下步骤：通过用激光照射基板来形成识别标记的第一元件，以相等的间隔平行地产生第一多个突起; 以及通过用激光照射所述基板来形成所述识别标记的另一元件，以与所述第一多个突起不重叠的相等间隔平行地产生第二多个突起。