公开(公告)号：US20120302054A1

公开(公告)日：2012-11-29

申请号：US13538891

申请日：2012-06-29

Applicant: Mark S. Johnson

Inventor： Mark S. Johnson

IPC: H01L21/768

CPC classification number: H05K3/428 ,  H01L21/4857 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0287 ,  H05K3/108 ,  H05K2201/09609 ,  H05K2201/10378

Abstract: Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate.

Abstract translation: 在此公开了使用这种方法形成的在和/或介入装置和微特征装置之间的导电结构的制造方法。 在一个实施例中，一种用于制造具有衬底的插入器器件的方法包括以第一图案在第一衬底上形成多个导电部分。 该方法通过在第二图案的第二基板上形成多个导电部分来继续。 该方法还包括在第一基板和第二基板上在公共第三图案中构造多条导线。 导电线可以在形成第一衬底上的第一导电部分图案之前或之后形成在第一衬底和第二衬底上，和/或在第二衬底上形成导电部分的第二图案。

公开(公告)号：US20120267153A1

公开(公告)日：2012-10-25

申请号：US13503581

申请日：2010-10-05

Applicant: Christian Solf

Inventor： Christian Solf

IPC: H05K1/18 ,  H05K3/30 ,  H05K1/11

CPC classification number: H05K1/0271 ,  B29C45/14 ,  H01L2924/0002 ,  H05K3/202 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/09118 ,  H05K2201/10151 ,  H05K2201/10378 ,  Y10T29/49146 ,  H01L2924/00

Abstract: The invention relates to a method for a coupling device (1) for connecting an electrical/electronic component (16), in particular a sensor (17), having a substrate, in particular a circuit board, wherein the coupling device (1) comprises at least one electrical connection (25) for electrical contacting and at least one damper element (12) for movement uncoupling, wherein the electrical connection is formed by a lead frame (3) and the lead frame (3) is overmolded in regions by a damping mass (11) as a damper element (12). The invention furthermore relates to an assembly having a coupling device and a method for producing said type of assembly.

Abstract translation: 本发明涉及一种用于连接电气/电子部件（16），特别是传感器（17）的耦合装置（1）的方法，该传感器具有基板，特别是电路板，其中联接装置（1）包括 用于电接触的至少一个电连接（25）和用于移动解耦的至少一个阻尼元件（12），其中所述电连接由引线框架（3）形成，并且所述引线框架（3）在区域中被二次模制 阻尼块（11）作为阻尼元件（12）。 本发明还涉及具有联接装置和用于生产所述类型组件的方法的组件。

公开(公告)号：US20120262875A1

公开(公告)日：2012-10-18

申请号：US13163502

申请日：2011-06-17

Applicant: Morgan Johnson ,  Frederick G. Weiss

Inventor： Morgan Johnson ,  Frederick G. Weiss

IPC: G06F1/16 ,  G06F1/20

CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.

Abstract translation: 插入器衬底包括插入器衬底中的互连阵列，所述连接器阵列根据用于电路衬底上的处理器的互连阵列布置，所述插入器衬底中的至少一个导电迹线与至少一个连接器 所述互连阵列，所述导电迹线平行于所述插入器基板布置，使得在所述插入器基板中的所述连接器与所述电路基板上的所述处理器的相应的一个互连件之间不存在电连接;以及至少一个外围电路， 所述插入器衬底与所述导电迹线电连接。

公开(公告)号：US20120250265A1

公开(公告)日：2012-10-04

申请号：US13525573

申请日：2012-06-18

Applicant: Toshiya KAWATE

Inventor： Toshiya KAWATE

IPC: H05K3/00 ,  H05K7/00

CPC classification number: H05K3/0052 ,  H01L23/5383 ,  H01L23/5385 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2924/09701 ,  H05K1/141 ,  H05K1/183 ,  H05K3/368 ,  H05K2201/10378 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49128

Abstract: A method of manufacturing a plurality of circuit modules includes cutting a mother board including a plurality of electronic components mounted on at least a single surface thereof, and cutting out a plurality of circuit boards from the mother board. A plurality of terminal electrode boards, each of which is arranged so as to straddle at least the circuit boards that are adjacent to each other, are mounted onto one surface of the mother board. The mother board including the terminal electrode boards mounted on the one surface, and the electronic components, mounted on the at least single surface, is diced at positions where the circuit boards are to be cut out.

Abstract translation: 一种制造多个电路模块的方法包括切割包括安装在其至少单个表面上的多个电子部件的母板，以及从母板切割多个电路板。 多个端子电极板被安装成至少跨越彼此相邻的电路板，安装在母板的一个表面上。 包括安装在一个表面上的端子电极板的母板和安装在至少单个表面上的电子部件在要切割电路板的位置被切割。

公开(公告)号：US08278565B2

公开(公告)日：2012-10-02

申请号：US12808107

申请日：2009-01-16

Applicant: Kazuhiko Honjo ,  Tadashi Nakamura

Inventor： Kazuhiko Honjo ,  Tadashi Nakamura

IPC: H05K1/11

CPC classification number: H05K3/462 ,  H05K1/183 ,  H05K3/4069 ,  H05K3/4697 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/09154 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/063 ,  H05K2203/068

Abstract: A three-dimensional circuit board includes a lower substrate, a connection layer provided on an upper surface of the lower substrate, and an upper substrate provided on an upper surface of the connection layer. The connection layer exposes a portion of the upper surface of the lower substrate. The connection layer includes an insulating layer having a through-hole, and a via-conductor made of conductive material filling the through-hole. A recess is provided directly above the portion of the upper surface of the lower substrate and is surrounded by a side surface of the upper substrate and a side surface of the connection layer. A portion of the upper surface of the connection layer connected to the side surface of the connection layer inclines in a direction toward the portion of the upper surface of the lower substrate. The portion of the upper surface of the connection layer is provided from the side surface of the connection layer to the via-conductor. A portion of an upper substrate of the upper substrate connected to the side surface of the upper substrate inclines in a direction toward the portion of the upper surface of the lower substrate. The circuit board allows a component to be mounted in the recess efficiently.

Abstract translation: 三维电路板包括下基板，设置在下基板的上表面上的连接层和设置在连接层的上表面上的上基板。 连接层露出下部基板的上表面的一部分。 连接层包括具有通孔的绝缘层和由填充通孔的导电材料制成的通孔导体。 在下基板的上表面的正上方设置凹部，被上基板的侧面和连接层的侧面包围。 连接到连接层的侧表面的连接层的上表面的一部分在朝向下基板的上表面的部分的方向上倾斜。 连接层的上表面的部分从连接层的侧表面提供到通孔导体。 连接到上基板的侧表面的上基板的上基板的一部分在朝向下基板的上表面的部分的方向上倾斜。 电路板允许组件有效地安装在凹槽中。

公开(公告)号：US20120243147A1

公开(公告)日：2012-09-27

申请号：US12904305

申请日：2010-10-14

Applicant: Francesco F. Marconi ,  Barry A. Bonitz ,  William E. Wilson

Inventor： Francesco F. Marconi ,  Barry A. Bonitz ,  William E. Wilson

IPC: H05K7/00 ,  B23K1/20 ,  H05K13/00 ,  B23K31/02

CPC classification number: H05K1/113 ,  B23K1/0016 ,  B23K1/20 ,  B23K26/361 ,  H01L21/4853 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2203/0315 ,  H01L2924/00

Abstract: A method of converting a land grid array (LGA) module to a ball grid array (BGA) module by removing and oxidizing portions of the LGA conductive pad features on the upper surface of the LGA module. A BGA solder ball is deposited on the remaining portion of the conductive feature of the LGA module, with subsequent reflowing of the BGA solder ball. By modifying the LGA module to support a BGA structure, excessive heat generated by components placed on the modified LGA pad can be conducted through the BGA structure and into the element on which the LGA module is attached, such as a PCB.

Abstract translation: 通过去除和氧化LGA模块的上表面上的LGA导电焊盘特征的部分，将焊盘格栅阵列（LGA）模块转换成球栅阵列（BGA）模块的方法。 BGA焊球沉积在LGA模块的导电特征的剩余部分上，随后BGA焊球回流。 通过修改LGA模块以支持BGA结构，放置在修改的LGA焊盘上的部件产生的过热可以通过BGA结构进入并连接到诸如PCB的LGA模块所连接的元件中。

公开(公告)号：US08274798B2

公开(公告)日：2012-09-25

申请号：US12845717

申请日：2010-07-28

Applicant: Shih-Jung Huang ,  Wen-Fang Liu ,  Ling-Kai Su

Inventor： Shih-Jung Huang ,  Wen-Fang Liu ,  Ling-Kai Su

IPC: H01R9/00

CPC classification number: H05K3/4015 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4007 ,  H05K2201/0311 ,  H05K2201/10378

Abstract: A carrier substrate includes a substrate having a chip side and a PCB side, a plurality of bond pads disposed on the chip side for bonding a chip, a plurality of land grid array (LGA) pads disposed on the PCB side, and a plurality of resilient flanges installed on the PCB side in an array manner. The plurality of resilient flanges electrically connects with the LGA pads correspondingly.

Abstract translation: 载体基板包括具有芯片侧和PCB侧的基板，设置在芯片侧的用于接合芯片的多个接合焊盘，设置在PCB侧的多个焊盘格栅阵列（LGA）焊盘，以及多个 弹性凸缘以阵列方式安装在PCB侧。 多个弹性凸缘相应地与LGA垫电连接。

公开(公告)号：US08263879B2

公开(公告)日：2012-09-11

申请号：US12614224

申请日：2009-11-06

Applicant: Gareth Hougham ,  Gerard McVicker ,  Xiaoxiong Gu ,  Sung K. Kang ,  Frank R. Libsch ,  Xiao H. Liu

Inventor： Gareth Hougham ,  Gerard McVicker ,  Xiaoxiong Gu ,  Sung K. Kang ,  Frank R. Libsch ,  Xiao H. Liu

IPC: H05K1/11

CPC classification number: H05K1/11 ,  H01R12/7082 ,  H01R12/714 ,  H01R13/2414 ,  H01R13/2421 ,  H01R43/16 ,  H05K3/326 ,  H05K3/4092 ,  H05K2201/0311 ,  H05K2201/10265 ,  H05K2201/10378 ,  Y10T29/49224 ,  Y10T29/49226

Abstract: A contact structure and assembly and a method for manufacturing the same for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

Abstract translation: 接触结构和组件及其制造方法用于微电子器件包括第一和第二导电接触件，其为螺旋形的。 载体元件附接到并定位在第一和第二触点之间。 第一和第二触点彼此电连通，并且第一和第二触点彼此成镜像关系。 一对绝缘基板各自包括导电构件。 每个第一和第二触点上的接触点被附接并与相应的导电构件电连通，使得该对绝缘基板之间的第一和第二导电触点形成导电封装。 载体元件上的金属层通过由载体元件在螺旋形接触件的第一和第二部分之间限定的第一开口提供导电性。

公开(公告)号：US20120162928A1

公开(公告)日：2012-06-28

申请号：US12910020

申请日：2010-10-22

Applicant: Rabindra N. Das ,  Frank D. Egitto ,  Voya R. Markovich

Inventor： Rabindra N. Das ,  Frank D. Egitto ,  Voya R. Markovich

IPC: H05K7/00 ,  H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49833 ,  H01L23/488 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2224/16225 ,  H05K1/111 ,  H05K1/144 ,  H05K3/06 ,  H05K3/368 ,  H05K3/4007 ,  H05K7/00 ,  H05K2201/0373 ,  H05K2201/042 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2203/047 ,  H05K2203/1572 ,  H05K2203/176 ,  Y10T29/49155

Abstract: An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates and also including an opening therein in which is positioned at least one electrical component, such as a semiconductor chip, coupled to the lower or base substrate. A second component may also be mounted on and electrically coupled to the upper surface of the top or cover circuitized substrate. A method of making such a package is also provided.

Abstract translation: 具有夹在其间的插入件的两个电路化基板的电子封装件，所述插入器将所述基板电连接并且还包括其中的开口，所述开口位于耦合到所述下基板或基底基板的至少一个电部件（例如半导体芯片）。 第二部件也可以安装在顶部或盖子电路化基板的上表面上并电耦合到顶部或盖子电路化基板的上表面。 还提供了制造这种包装的方法。

公开(公告)号：US20120147567A1

公开(公告)日：2012-06-14

申请号：US12964503

申请日：2010-12-09

Applicant: Yun-Han Lee ,  Mark Shane Peng ,  Shyh-An Chi

Inventor： Yun-Han Lee ,  Mark Shane Peng ,  Shyh-An Chi

IPC: H05K7/00

CPC classification number: H05K1/181 ,  H01L23/147 ,  H01L23/538 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2225/06565 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K2201/10045 ,  H05K2201/10053 ,  H05K2201/10378 ,  H01L2924/00

Abstract: A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.

Abstract translation: 一种包装结构包括一个包括多个交换机/路由器的联网单元和耦合到该多个交换机/路由器的多个网络接口单元，以及包括多个金属连接的插件。 内插器基本上没有内置的功能元件。 功能元件在插入器之外并且结合到插入器上，其中功能元件通过多个金属连接电耦合到联网单元。