公开(公告)号：US20110155440A1

公开(公告)日：2011-06-30

申请号：US12783837

申请日：2010-05-20

Applicant: Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K3/107 ,  H05K3/421 ,  H05K2201/0376 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board including a circuit substrate, a dielectric layer, a first conductive layer and a second conductive layer is provided. The circuit substrate has a first surface and a first circuit layer. The dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The dielectric layer has a second surface, at least a blind via extended from the second surface to the first circuit layer and an intaglio pattern. The first conductive layer is disposed inside the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer through the first conductive layer.

Abstract translation: 提供了包括电路基板，电介质层，第一导电层和第二导电层的电路板。 电路基板具有第一表面和第一电路层。 电介质层设置在电路基板上并覆盖第一表面和第一电路层。 电介质层具有第二表面，至少从第二表面延伸到第一电路层的盲孔和凹版图案。 第一导电层设置在盲孔内。 第二导电层设置在凹版图案和盲孔中并覆盖第一导电层。 第二导电层通过第一导电层与第一电路层电连接。

公开(公告)号：US20110116248A1

公开(公告)日：2011-05-19

申请号：US13006222

申请日：2011-01-13

Applicant: Tsugio AMBO ,  Satoru Fujiwara ,  Yoshikatsu Hasegawa ,  Chihiro Nakagawa ,  Takeshi Ono ,  Atsushi Urushidani ,  Tooru Kashioka ,  Katsuji Shimazawa

Inventor： Tsugio AMBO ,  Satoru Fujiwara ,  Yoshikatsu Hasegawa ,  Chihiro Nakagawa ,  Takeshi Ono ,  Atsushi Urushidani ,  Tooru Kashioka ,  Katsuji Shimazawa

IPC: H05K7/00

CPC classification number: H05K3/202 ,  H01R9/2466 ,  H01R12/523 ,  H05K3/041 ,  H05K3/222 ,  H05K3/308 ,  H05K3/326 ,  H05K3/328 ,  H05K3/4046 ,  H05K3/4611 ,  H05K13/0061 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/091 ,  H05K2201/096 ,  H05K2201/10287 ,  H05K2201/10401 ,  H05K2201/1059 ,  H05K2201/10598 ,  H05K2203/081 ,  H05K2203/082 ,  H05K2203/167 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T428/24917

Abstract: A circuit board includes a foil circuit provided on a synthetic resin plate formed by injection molding, made of a copper foil, and having a pattern different for the circuit board. Anchor pins projecting upward are provided on the resin plate and passed through pinholes made in the foil circuit. The foil circuit is positioned and secured to the resin plate. In a required portion of the resin plate, a terminal insertion hole is provided, and a receiving terminal is secured to the required portion of the terminal insertion hole and connected to the foil circuit.

Abstract translation: 电路板包括设置在通过注射成型形成的合成树脂板上的箔电路，由铜箔制成并且具有不同于电路板的图案。 在树脂板上设置向上突出的定位销，并穿过箔片电路中制成的针孔。 箔片电路定位并固定到树脂板上。 在树脂板的所需部分中，设置有端子插入孔，并且接收端子固定到端子插入孔的所需部分并连接到箔片电路。

公开(公告)号：US07891091B2

公开(公告)日：2011-02-22

申请号：US12315066

申请日：2008-11-25

Applicant: Yonggang Li ,  Islam Salama

Inventor： Yonggang Li ,  Islam Salama

IPC: H01K3/10

CPC classification number: H05K3/107 ,  H05K3/0038 ,  H05K3/027 ,  H05K3/108 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09563 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of enabling selective area plating on a substrate (201) includes forming a first electrically conductive layer (310) on the substrate, covering the electrically conductive layer with an anti-electroless plating layer (410), patterning the substrate in order to form therein a feature (510, 520) extending through the anti-electroless plating layer and the first electrically conductive layer, forming a second electrically conductive layer (610) adjoining and electrically connected to the first electrically conductive layer, forming a third electrically conductive layer (710) over the second electrically conductive layer, and removing the anti-electroless plating layer and the first electrically conductive layer.

Abstract translation: 在衬底（201）上进行选择性区域电镀的方法包括在衬底上形成第一导电层（310），用抗化学镀层（410）覆盖导电层，图案化衬底以形成 其中延伸穿过抗化学镀层和第一导电层的特征（510,520），形成邻接并电连接到第一导电层的第二导电层（610），形成第三导电层（ 710），并且去除所述防电镀层和所述第一导电层。

公开(公告)号：US20110024176A1

公开(公告)日：2011-02-03

申请号：US12559443

申请日：2009-09-14

Applicant: Young Gwan Ko

Inventor： Young Gwan Ko

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/4682 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/0097 ,  H05K3/045 ,  H05K2201/0376 ,  H05K2203/0108 ,  H05K2203/0733 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Disclosed is a printed circuit board, which includes an insulating member having a circuit pattern embedded in one surface thereof, a build-up layer formed on one surface of the insulating member and including a build-up insulating layer and a circuit layer formed in the build-up insulating layer and having a via connected to the circuit pattern, and a solder resist layer formed on the build-up layer. A method of fabricating the printed circuit board is also provided. The printed circuit board is fabricated using a build-up process and the outermost circuit layer thereof is formed to have an embedded structure using an imprinting process, thus minimizing the separation of the circuit layer and reducing the lead time and the fabrication cost.

Abstract translation: 公开了一种印刷电路板，其包括具有嵌入其一个表面中的电路图案的绝缘构件，形成在所述绝缘构件的一个表面上并包括积聚绝缘层和形成在所述绝缘构件中的电路层的积聚层 并且具有连接到电路图案的通孔，以及形成在积聚层上的阻焊层。 还提供了制造印刷电路板的方法。 印刷电路板使用积聚工艺制造，并且其最外面的电路层被形成为具有使用压印工艺的嵌入式结构，从而最小化电路层的分离并减少了交货时间和制造成本。

公开(公告)号：US20100295191A1

公开(公告)日：2010-11-25

申请号：US12811733

申请日：2009-01-06

Applicant: Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

Inventor： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

IPC: H01L23/49 ,  H01L21/60 ,  H05K1/11 ,  H01R43/00

CPC classification number: H05K3/4647 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2203/0733 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.

Abstract translation: 在布线板中，绝缘层和布线层交替层叠，并且布线层通过通孔电连接。 布线基板包括布置在第一表面中并嵌入绝缘层中的第一端子，布置在与第一表面相对的第二表面中并嵌入绝缘层中的第二端子，以及布置在绝缘层中并与第一端子接触的焊盘 终端。 通孔将焊盘和与绝缘层交替层压的布线层电连接。 在接地侧的每个通孔的端部没有形成连接接口，但是在布线层侧的每个通孔的端部形成有连接接口。

公开(公告)号：US07824838B2

公开(公告)日：2010-11-02

申请号：US12068125

申请日：2008-02-01

Applicant: Ji-Hong Jo ,  Shuhichi Okabe

Inventor： Ji-Hong Jo ,  Shuhichi Okabe

IPC: G03F7/00 ,  G03F7/26 ,  G03F7/40

CPC classification number: H05K3/205 ,  H05K3/045 ,  H05K3/107 ,  H05K2201/0376 ,  H05K2203/0108 ,  H05K2203/0113 ,  H05K2203/0117

Abstract: A method of manufacturing a printed circuit board is disclosed. The method includes: forming a relievo pattern and an intaglio pattern on a surface of a base plate; forming a metal plate, which has a metal pattern that corresponds with a shape of the relievo pattern and the intaglio pattern, by plating a surface of the relievo pattern and a surface of the intaglio pattern; separating the metal plate from the base plate; pressing the metal plate onto an insulation layer with the metal pattern facing the insulation layer; and removing a portion of the metal plate such that the metal pattern is exposed. Since this method does not use carriers, there is no need for a chemical etching process for carrier removal.

Abstract translation: 公开了一种制造印刷电路板的方法。 该方法包括：在基板的表面上形成解除图案和凹版图案; 通过电镀所述消光图案的表面和所述凹版图案的表面，形成金属板，所述金属板具有与所述缓和图案和所述凹版图案的形状相对应的金属图案; 将金属板与基板分离; 将金属板压在绝缘层上，金属图案面向绝缘层; 以及去除所述金属板的一部分以使得所述金属图案露出。 由于该方法不使用载体，因此不需要用于载体去除的化学蚀刻方法。

公开(公告)号：US07755183B2

公开(公告)日：2010-07-13

申请号：US11084805

申请日：2005-03-18

Applicant: Mitsuhiko Yamamoto

Inventor： Mitsuhiko Yamamoto

IPC: H01L23/48

CPC classification number: H05K1/0265 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/111 ,  H05K3/205 ,  H05K3/244 ,  H05K3/245 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2201/09881 ,  H01L2924/00 ,  H01L2224/0401

Abstract: According to this invention, a wiring board includes a conductive pattern formed from leads each of which is formed on an organic layer and has a thickness t larger than a width W.

Abstract translation: 根据本发明，布线基板包括由引线形成的导电图案，每个引线形成在有机层上并且具有大于宽度W的厚度t

公开(公告)号：US20100052993A1

公开(公告)日：2010-03-04

申请号：US12361781

申请日：2009-01-29

Applicant: Heung-Kyu KIM

Inventor： Heung-Kyu KIM

IPC: H01P3/08

CPC classification number: H01P3/081 ,  H01P11/003 ,  H05K1/0221 ,  H05K3/205 ,  H05K2201/0376 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09827

Abstract: A printed circuit board having a micro strip line, a printed circuit board having a strip line and a method of manufacturing thereof are disclosed. The printed circuit board having a micro strip line in accordance with an embodiment of the present invention includes a first insulation layer, a signal line buried in one surface of the first insulation layer, a plurality of conductors penetrating through the first insulation layer and being disposed on both sides of the signal line in parallel with the signal line, and a ground layer formed to be electrically connected to the conductor on the other surface of the first insulation layer.

Abstract translation: 公开了一种具有微带线的印刷电路板，具有带状线的印刷电路板及其制造方法。 根据本发明的实施例的具有微带线的印刷电路板包括第一绝缘层，埋在第一绝缘层的一个表面中的信号线，穿过第一绝缘层的多个导体，并被布置 在与信号线并联的信号线的两侧，以及形成为与第一绝缘层的另一个表面上的导体电连接的接地层。

公开(公告)号：US20100002406A1

公开(公告)日：2010-01-07

申请号：US12496136

申请日：2009-07-01

Applicant: Shin-Ping Hsu

Inventor： Shin-Ping Hsu

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/2518 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/18162 ,  H05K3/4602 ,  H05K3/465 ,  H05K2201/0376 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A circuit board having a semiconductor chip embedded therein includes: a core board having opposing first and second surfaces and a through-hole; a semiconductor chip received in the through-hole and having a first active surface and an opposing second active surface, wherein first electrode pads comprising signal pads, power pads, and ground pads are provided on the first active surface; a first dielectric layer provided on the first surface of the core board and the first active surface of the semiconductor chip and configured to fill a gap between the through-hole and the semiconductor chip so as to secure the semiconductor chip in position to the through-hole; and a first circuit layer disposed in the first dielectric layer so as to be flush with the first dielectric layer, provided with first conductive vias disposed in the first dielectric layer, and electrically connected to the first electrode pads.

Abstract translation: 具有嵌入其中的半导体芯片的电路板包括：具有相对的第一和第二表面的芯板和通孔; 半导体芯片，其被容纳在所述通孔中并且具有第一有源表面和相对的第二有源表面，其中包括信号焊盘，功率焊盘和接地焊盘的第一电极焊盘设置在所述第一有源表面上; 设置在所述芯板的第一表面和所述半导体芯片的所述第一有源表面上并且被配置为填充所述通孔和所述半导体芯片之间的间隙的第一介电层，以将所述半导体芯片固定在通孔的位置， 孔; 以及第一电路层，设置在第一电介质层中以与第一电介质层齐平，设置有设置在第一介电层中的第一导电通孔，并且电连接到第一电极焊盘。

公开(公告)号：US20090308640A1

公开(公告)日：2009-12-17

申请号：US12232253

申请日：2008-09-12

Applicant: Won Kyu Jeung ,  Yi Sung

Inventor： Won Kyu Jeung ,  Yi Sung

IPC: H05K1/03 ,  H05K3/36

CPC classification number: H05K3/4629 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/0376 ,  H05K2201/0949 ,  H05K2201/10378 ,  Y10T29/49126 ,  H01L2924/00

Abstract: Provided is a wafer level package including a first substrate that has circuit patterns provided on the top surface thereof and first vias formed therein, the first vias being electrically connected to the circuit patterns; and a second substrate that is bonded to the bottom surface of the first substrate through anodic bonding and has second vias formed therein.

Abstract translation: 提供了一种晶片级封装，其包括具有设置在其顶表面上的电路图案的第一基板和形成在其中的第一通孔，第一通孔电连接到电路图案; 以及第二基板，其通过阳极接合而结合到第一基板的底表面，并且具有形成在其中的第二通孔。