公开(公告)号：US20070149057A1

公开(公告)日：2007-06-28

申请号：US11522530

申请日：2006-09-18

Applicant: Thomas Cohen ,  Marc Cartier ,  Mark Gailus

Inventor： Thomas Cohen ,  Marc Cartier ,  Mark Gailus

IPC: H01R13/648

CPC classification number: H05K7/1445 ,  H01R13/514 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

Abstract translation: 中平面具有连接第一差分连接器的接触端的第一侧和与第二差分连接器的接触端连接的第一侧相对的第二侧。 中平面包括从第一侧延伸到第二侧的多个通孔，其中通孔在第一侧上提供第一信号发射，而第二信号在第二侧上发射。 第一信号发射被设置成多行，每行具有沿着第一线的第一信号发射，并且第一信号沿着基本上平行于第一线的第二线发射。 第二信号发射被提供在多列中，每列具有沿着第三线的第二信号发射，而第二信号沿着基本上平行于第三线的第四线发射。

公开(公告)号：US07227759B2

公开(公告)日：2007-06-05

申请号：US11097450

申请日：2005-04-01

Applicant: Kevin P. Grundy ,  Gary Yasumura ,  Joseph C. Fjelstad ,  William F. Wiedemann ,  Para K. Segaram

Inventor： Kevin P. Grundy ,  Gary Yasumura ,  Joseph C. Fjelstad ,  William F. Wiedemann ,  Para K. Segaram

IPC: H01R12/16

CPC classification number: H01R12/52 ,  H01R12/7011 ,  H01R12/7082 ,  H01R12/714 ,  H01R12/716 ,  H01R12/721 ,  H01R13/24 ,  H01R31/06 ,  H05K1/0237 ,  H05K1/14 ,  H05K1/147 ,  H05K3/222 ,  H05K7/1441 ,  H05K2201/044 ,  H05K2201/10189 ,  H05K2201/10356

Abstract: A signal-segregating connector for use in a system having a printed circuit board, a first electrical structure and a second electrical structure. The connector includes a first set of conductive elements to convey signals between the first electrical structure and the printed circuit board, and a second set of conductive elements to convey signals between the first electrical structure and the second electrical structure.

Abstract translation: 一种用于具有印刷电路板，第一电气结构和第二电气结构的系统中的信号分离连接器。 连接器包括用于在第一电气结构和印刷电路板之间传送信号的第一组导电元件和用于在第一电结构和第二电结构之间传送信号的第二组导电元件。

公开(公告)号：US07209987B1

公开(公告)日：2007-04-24

申请号：US10976516

申请日：2004-10-29

Applicant: Eric D. Schneider ,  Gary Nachazel ,  John Ryan

Inventor： Eric D. Schneider ,  Gary Nachazel ,  John Ryan

IPC: G06F13/40 ,  G06F13/00 ,  H01L25/00 ,  G06F13/42

CPC classification number: H05K1/14 ,  G06F13/409 ,  H05K1/0286 ,  H05K2201/044 ,  H05K2201/10212

Abstract: Provided are a method and a system for designing an embedded system using a design process for building a general-purpose computer. Specifically, the embedded system design includes adding and removing add-on cards as needed during the development of the embedded system design. The add-on cards are easily obtainable and connect to a circuit board of the embedded system by selecting lines originating from the circuit board. The lines not selected are passed on to other add-on cards connected to previously connected add-on cards. After all the lines from the circuit board are either selected to connect to logic of the add-on cards or remain unselected, information regarding the add-on cards are used to generate a configuration image. The configuration image is transmitted to a programmable processor of the circuit board to enable communication on the selected lines, thus permitting the embedded system to function.

Abstract translation: 提供了一种使用设计过程来构建通用计算机来设计嵌入式系统的方法和系统。 具体来说，嵌入式系统设计包括在嵌入式系统设计开发过程中根据需要添加和删除附加卡。 通过选择源自电路板的线路，可以轻松获得附加卡并连接到嵌入式系统的电路板。 未选择的行传递到连接到先前连接的附加卡上的其他附加卡。 在选择所有来自电路板的线路以连接到附加卡的逻辑或保持未选择之后，关于附加卡的信息用于生成配置图像。 将配置图像发送到电路板的可编程处理器，以使得能够在所选择的线路上进行通信，从而允许嵌入式系统起作用。

公开(公告)号：US07202681B2

公开(公告)日：2007-04-10

申请号：US10928385

申请日：2004-08-27

Applicant: Steven J. Brunelle ,  Saeed Momenpour

Inventor： Steven J. Brunelle ,  Saeed Momenpour

IPC: G01R31/02 ,  G01R31/28

CPC classification number: H05K7/1431 ,  G11C5/04 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H05K1/14 ,  H05K1/147 ,  H05K3/222 ,  H05K2201/044 ,  H05K2201/10159 ,  H05K2201/10325 ,  H05K2203/162

Abstract: A testing apparatus, system and method for testing computer memory modules are disclosed. The apparatus includes a motherboard having a processor and at least one resident memory socket fixed to the motherboard. A remote memory socket is provided and located a distance from the resident memory socket, such as on a periphery of the motherboard. The remote memory socket is coupled to the resident memory socket by a conductor assembly such as a ribbon cable and an adapter. A memory module is placed in the remote memory socket and tested using a signal or combination of signals from the processor. A plurality of motherboards, each being configured with remote memory sockets, may be combined to form a testing system suitable for use with an automated handler.

Abstract translation: 公开了一种用于测试计算机存储器模块的测试装置，系统和方法。 该装置包括具有处理器的主板和固定到主板的至少一个驻留存储器插槽。 提供远程存储器插座，并且与驻留的存储器插座（例如在主板的外围）上定位一定距离。 远程存储器插座通过诸如带状电缆和适配器的导体组件耦合到驻留的存储器插槽。 存储器模块放置在远程存储器插槽中，并使用来自处理器的信号或信号的组合进行测试。 每个配置有远程存储器插槽的多个主板可以组合以形成适合于与自动处理程序一起使用的测试系统。

公开(公告)号：US07151675B2

公开(公告)日：2006-12-19

申请号：US10639464

申请日：2003-08-13

Applicant: Yuichiro Murata ,  Naoki Nakagawa

Inventor： Yuichiro Murata ,  Naoki Nakagawa

IPC: H01R12/16

CPC classification number: H05K1/14 ,  H05K1/023 ,  H05K1/167 ,  H05K2201/044 ,  H05K2201/10022

Abstract: A multi-pin connector for connecting a signal line on a backboard side and a signal line on a daughter board side has open pins where the signal lines are not connected. In order to prevent transmission loss on the signal lines caused by these open pins, terminating resistances are connected to both ends of the open pins, and ends of the terminating resistances opposite to the open pins are connected to ground or to a power supply.

Abstract translation: 用于连接背板侧的信号线和子板侧的信号线的多针连接器具有未连接信号线的开路引脚。 为了防止由这些开放引脚引起的信号线上的传输损耗，端接电阻连接到开放引脚的两端，并且与开路引脚相反的端接电阻的端部连接到地或电源。

公开(公告)号：US07133297B2

公开(公告)日：2006-11-07

申请号：US10825236

申请日：2004-04-16

Applicant: Long-Kun Yu ,  Yao-Hui Wu

Inventor： Long-Kun Yu ,  Yao-Hui Wu

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0246 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022

Abstract: A slot apparatus for a memory module on a printed circuit board. The slot apparatus includes a first memory slot set, a second memory slot set, a terminal resistor, and a serial resistance. The first and second memory slot sets are disposed on the printed circuit board. The terminal resistor is disposed between the first and second memory slot sets. The serial resistance is disposed on the printed circuit board and is electrically connected to the first and second memory slot sets through the printed circuit board. The terminal resistor is respectively and electrically connected to the first and second memory slot sets through the printed circuit board. The terminal resistor and the first and second memory slot sets are connected to a terminator voltage.

Abstract translation: 一种用于印刷电路板上的存储器模块的槽设备。 插槽装置包括第一存储器插槽组，第二存储器插槽组，终端电阻器和串联电阻器。 第一和第二存储器插槽组设置在印刷电路板上。 端子电阻器设置在第一和第二存储器插槽组之间。 串联电阻设置在印刷电路板上，并且通过印刷电路板电连接到第一和第二存储器插槽组。 端子电阻器通过印刷电路板分别电连接到第一和第二存储器插槽组。 端子电阻器和第一和第二存储器插槽组连接到终端电压。

公开(公告)号：US07124502B2

公开(公告)日：2006-10-24

申请号：US10917553

申请日：2004-08-11

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01K3/22

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

公开(公告)号：US20060221587A1

公开(公告)日：2006-10-05

申请号：US11442253

申请日：2006-05-30

Applicant: Yoshihiro Morita

Inventor： Yoshihiro Morita

IPC: H05K1/14 ,  H01R12/16

CPC classification number: H05K1/028 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01R12/714 ,  H05K1/147 ,  H05K3/103 ,  H05K3/4691 ,  H05K2201/0394 ,  H05K2201/044 ,  H05K2201/10189 ,  H05K2201/10287 ,  Y10T29/49169 ,  Y10T29/49194 ,  H01L2224/0401

Abstract: A multi-wire board includes first and second substrates, and plural wires that connect the first and second substrates to each other, and expose to the outside, wherein the wires form a predetermined pattern in the first substrate.

Abstract translation: 多线基板包括第一和第二基板以及将第一和第二基板彼此连接并且暴露于外部的多根电线，其中电线在第一基板中形成预定图案。

公开(公告)号：US20060158864A1

公开(公告)日：2006-07-20

申请号：US11037596

申请日：2005-01-18

Applicant: Raphael Gay

Inventor： Raphael Gay

IPC: H05K7/10

CPC classification number: G06F1/185 ,  G06F13/409 ,  H05K1/0295 ,  H05K1/111 ,  H05K3/366 ,  H05K2201/044 ,  H05K2201/09954 ,  H05K2201/10189

Abstract: A circuit board comprising at least one slot provided on a surface of the circuit board. An add-in card can be mated to the slot. The slot comprises a first electrical connection adapted to couple to an add-in card of a first type and a second electrical connection adapted to couple to an add-in card of a second type. The first or second types of add-in cards are different.

Abstract translation: 一种电路板，包括设置在电路板的表面上的至少一个槽。 附加卡可以与插槽配合使用。 插槽包括适于耦合到第一类型的附加卡的第一电连接和适于耦合到第二类型的附加卡的第二电连接。 第一种或第二种类型的附加卡是不同的。

公开(公告)号：US07035116B2

公开(公告)日：2006-04-25

申请号：US10715145

申请日：2003-11-17

Applicant: Maksim Kuzmenka

Inventor： Maksim Kuzmenka

IPC: H01R12/16 ,  H05K1/11 ,  G06F1/16

CPC classification number: H05K1/147 ,  G11C5/00 ,  H05K1/148 ,  H05K3/222 ,  H05K2201/044

Abstract: A memory system has a circuit board provided with a first slot connector into which a first memory module is inserted. A second slot connector is provided into which a second memory module is inserted. The first and the second memory modules are connected via a flexible bridge. The flexible bridge extends from respective ends of the memory modules opposite to that ends thereof which are inserted into the connector slots. The flexible bridge provides a signal bus between the memory modules.

Abstract translation: 存储器系统具有设置有第一存储器模块插入其中的第一槽连接器的电路板。 提供第二插槽连接器，插入第二存储器模块。 第一和第二存储器模块通过柔性桥连接。 所述柔性桥从所述存储器模块的与其端部相对的端部延伸，所述端部插入所述连接器槽中。 灵活的桥接器在存储器模块之间提供信号总线。