公开(公告)号：US20240126313A1

公开(公告)日：2024-04-18

申请号：US18079900

申请日：2022-12-13

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Chih Ku

IPC: G06F1/3234 ,  G06F1/3296

CPC classification number: G06F1/3275 ,  G06F1/3296

Abstract: A regulator circuit module, a memory storage device, and a voltage control method are disclosed. The method includes: generating an output voltage according to an input voltage by a driving circuit; generating a feedback voltage according to the output voltage; controlling the driving circuit to adjust the output voltage according to the feedback voltage by a regulator circuit; compensating an output of the regulator circuit by a compensating circuit; and activating or deactivating the compensating circuit according to an input bypass-voltage of a switch circuit.

公开(公告)号：US11809706B2

公开(公告)日：2023-11-07

申请号：US17349918

申请日：2021-06-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Wei Lin ,  An-Cheng Liu

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.

公开(公告)号：US20230297464A1

公开(公告)日：2023-09-21

申请号：US17715050

申请日：2022-04-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F11/07 ,  G06F1/30 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F1/30 ,  G06F11/073 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0689 ,  G06F3/0619

Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.

公开(公告)号：US20230297233A1

公开(公告)日：2023-09-21

申请号：US17721358

申请日：2022-04-15

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

Abstract: A memory management method configured for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit are provided. The rewritable non-volatile memory module includes a plurality of dies, wherein each of the dies includes a plurality of planes, each of the planes includes a plurality of physical erasing units, and a sum of a number of the planes included in the rewritable non-volatile memory module is a first number. The method includes: grouping the plurality of physical erasing units into a plurality of management units. Each of the plurality of physical erasing units included in each of the management units belongs to a different plane, and each of the management units has a second number of the physical erasing units, wherein the second number is less than the first number.

公开(公告)号：US20230289102A1

公开(公告)日：2023-09-14

申请号：US17724504

申请日：2022-04-20

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Bo Lun Huang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: An encoding control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing, by an encoding circuit, a first encoding operation to generate first parity data according to write data, a first sub-matrix and a second sub-matrix of a parity check matrix; performing, by the encoding circuit, a second encoding operation to generate second parity data according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix and a fifth sub-matrix of the parity check matrix; and sending a first write command sequence to instruct a storing of the write data, the first parity data and the second parity data to a rewritable non-volatile memory module.

公开(公告)号：US11757684B2

公开(公告)日：2023-09-12

申请号：US17543741

申请日：2021-12-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chun-Wei Chang ,  Ching-Jui Hsiao ,  Jen-Chu Wu ,  Yuwei Kuo

IPC: H04L25/49

CPC classification number: H04L25/4904

Abstract: A retiming circuit module, a signal transmission system, and a signal transmission method are provided. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes built-in first signal transmission path and second signal transmission path. The multipath signal transmission circuit may perform first signal transmission between an upstream device and a downstream device based on a first signal transmission frequency and the second signal transmission path. During a period of performing the first signal transmission, the path control circuit may detect a first data sequence transmitted between the upstream device and the downstream device. The path control circuit may control the multipath signal transmission circuit to switch to perform second signal transmission between the upstream device and the downstream device based on the first signal transmission frequency and the first signal transmission path according to the first data sequence.

公开(公告)号：US11755242B2

公开(公告)日：2023-09-12

申请号：US16988731

申请日：2020-08-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Che-Yueh Kuo ,  Li Hsun Lien

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/065 ,  G06F3/0679 ,  G06F12/1009 ,  G06F2212/657

Abstract: A data merging method can copy a new logical to physical mapping table and update a copied logical to physical mapping table according to a physical address of a recycling unit expected to be written at the same time. In this way, the number of times that the same logic to physical mapping table is read multiple times during the data merging operation can be reduced to improve the execution efficiency of the data merging operation, thereby increasing the system performance of the memory storage device.

公开(公告)号：US20230035428A1

公开(公告)日：2023-02-02

申请号：US17458548

申请日：2021-08-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Jung Chou ,  Sheng-Wen Chen ,  Chung-Kuang Chen

IPC: G06F1/26 ,  G06F13/40

Abstract: A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.

公开(公告)号：US11561719B2

公开(公告)日：2023-01-24

申请号：US17242240

申请日：2021-04-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Wei Lin ,  An-Cheng Liu ,  Yu-Heng Liu ,  Chun-Hsi Lai ,  Ting-Chien Zhan

IPC: G06F3/06

Abstract: A flash memory control method, a flash memory storage device and a flash memory controller are provided. The method includes the following. A flash memory module is instructed to perform a data merge operation to copy first data in a first physical unit into at least one second physical unit. After the first data is copied and before the first physical unit is erased, another programming operation is performed on the first physical unit to change a data storage state of at least a part of memory cells in the first physical unit from a first state into a second state. After the first physical unit is programmed, an erase operation is performed on the first physical unit.

公开(公告)号：US20220334920A1

公开(公告)日：2022-10-20

申请号：US17306896

申请日：2021-05-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hsiao-Chi Ho

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  G06F11/30 ,  G06F12/02

Abstract: A method for managing a host memory buffer, a memory storage apparatus, and a memory control circuit unit are provided. The method includes: detecting whether a system abnormality occurs; copying a first command and first data corresponding to the first command stored in a data buffer of a host system to the memory storage apparatus in response to determining that the system abnormality occurs; executing an initial operation after copying the first command and the first data, wherein the initial operation initializes a part of a hardware circuit in the memory storage apparatus and does not initialize another part of the hardware circuit in the memory storage apparatus; and re-executing the first command stored in the memory storage apparatus after initializing the part of the hardware circuit.