公开(公告)号：US20150262869A1

公开(公告)日：2015-09-17

申请号：US14276879

申请日：2014-05-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Mehul B. NAIK ,  Srinivas D. NEMANI ,  Takehito KOSHIZAWA ,  He REN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L21/32136 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/3244 ,  H01L21/02071 ,  H01L21/02274 ,  H01L21/32139 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76885

Abstract: Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.

Abstract translation: 本发明的实施例提供了在半导体器件中形成互连结构而不破坏最小氧化/大气暴露的真空的方法。 在一个实施例中，用于形成用于半导体器件的互连结构的方法包括将阻挡层蚀刻气体混合物供应到具有设置在其中的衬底的第一处理室中，以蚀刻由图案化金属层暴露的阻挡层的部分，直到下面的衬底为 暴露的第一处理室，设置在处理系统中，并且在布置在处理系统中的第二处理室中，在覆盖蚀刻的阻挡层的基板上形成衬垫层。

公开(公告)号：US20150221596A1

公开(公告)日：2015-08-06

申请号：US14173807

申请日：2014-02-05

Applicant: APPLIED MATERIALS, INC.

Inventor： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Mei-Yee SHEK ,  Yana Cheng ,  Sree Rangasai V. Kesapragada

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.

Abstract translation: 描述了用于半导体器件的互连结构及其制造方法。 该方法包括将基板定位在真空处理室中。 衬底具有暴露的铜表面和暴露的低k电介质表面。 在铜表面上形成金属层，但不在低k电介质表面上。 在金属层和低k电介质层上形成金属基介电层。

公开(公告)号：US20220181201A1

公开(公告)日：2022-06-09

申请号：US17110826

申请日：2020-12-03

Applicant: Applied Materials, Inc.

Inventor： Yi XU ,  Yufei HU ,  He REN ,  Yu LEI ,  Shi YOU ,  Kazuya DAITO

IPC: H01L21/768

Abstract: Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.

公开(公告)号：US20210074583A1

公开(公告)日：2021-03-11

申请号：US16562091

申请日：2019-09-05

Applicant: Applied Materials, Inc.

Inventor： Shi YOU ,  He REN ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments of the present disclosure generally relate an interconnect structure formed on a substrate and a method of forming the interconnect structure thereon. In one embodiment, a method of forming an interconnect structure includes forming an opening comprising a via and a trench in an insulating structure formed on a substrate, forming a first passivation layer in the opening, removing a portion of the first passivation layer from the opening, and selectively depositing a first metal containing material in the via.

公开(公告)号：US20210066064A1

公开(公告)日：2021-03-04

申请号：US17004850

申请日：2020-08-27

Applicant: APPLIED MATERIALS, INC.

Inventor： He REN ,  Shi YOU ,  Hao JIANG ,  Raymond HUNG ,  Mehul NAIK ,  Chentsau Chris YING ,  Mang-Mang LING ,  Lin DONG

IPC: H01L21/02

Abstract: Methods and apparatus for cleaning a contaminated metal surface on a substrate, including: exposing a substrate including a dielectric surface and a metal surface including metal nitride residues and metal carbide residues to a process gas including an oxidizing agent to form a substrate including a dielectric surface and a metal surface including metal oxides residues; and exposing a substrate including a dielectric surface and a metal surface including metal oxides residues to a process gas including a reducing agent to form a substrate including a dielectric surface and a substantially pure metal surface.

公开(公告)号：US20200303250A1

公开(公告)日：2020-09-24

申请号：US16803842

申请日：2020-02-27

Applicant: Applied Materials, Inc.

Inventor： Xi CEN ,  Feiyue MA ,  Kai WU ,  Yu LEI ,  Kazuya DAITO ,  Yi XU ,  Vikash BANTHIA ,  Mei CHANG ,  He REN ,  Raymond Hoiman HUNG ,  Yakuan YAO ,  Avgerinos V. GELATOS ,  David T. OR ,  Jing ZHOU ,  Guoqiang JIAN ,  Chi-Chou LIN ,  Yiming LAI ,  Jia YE ,  Jenn-Yue WANG

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/02

Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.

公开(公告)号：US20190311908A1

公开(公告)日：2019-10-10

申请号：US16366539

申请日：2019-03-27

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Maximillian CLEMONS ,  Mei-Yee SHEK ,  Minrui YU ,  Bencherki MEBARKI ,  Mehul B. NAIK ,  Chentsau YING ,  Srinivas D. NEMANI

IPC: H01L21/285 ,  H01L29/45

Abstract: Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.

公开(公告)号：US20190189433A1

公开(公告)日：2019-06-20

申请号：US16237407

申请日：2018-12-31

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Yana CHENG ,  Weifeng YE

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/02167 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/76826 ,  H01L21/76832

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

公开(公告)号：US20150140827A1

公开(公告)日：2015-05-21

申请号：US14541978

申请日：2014-11-14

Applicant: Applied Materials, Inc.

Inventor： Chia-Ling KAO ,  Sean KANG ,  Jeremiah T. PENDER ,  Srinivas D. NEMANI ,  He REN ,  Mehul NAIK

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01J37/32449 ,  H01J37/32477 ,  H01J37/32834 ,  H01J37/32871 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Abstract translation: 本文描述的实施方式通常涉及半导体制造，更具体地涉及使用非碳基方法蚀刻设置在基板上的低k电介质阻挡层的方法。 在一个实施方案中，提供了用于蚀刻阻挡层低k层的方法。 该方法包括（a）将低k阻挡层的表面暴露于处理气体混合物以修饰低k阻挡层的至少一部分，和（b）化学蚀刻低k阻挡层的修饰部分 通过将改性部分暴露于化学蚀刻气体混合物，其中化学蚀刻气体混合物至少包含铵气体和三氟化氮气体，或至少包含氢气和三氟化氮气体。

公开(公告)号：US20250157851A1

公开(公告)日：2025-05-15

申请号：US18835577

申请日：2023-02-13

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Houssam LAZKANI ,  Raman GAIRE ,  Mehul NAIK ,  Kuan-Ting LIU

IPC: H01L21/74 ,  H01L21/02 ,  H01L23/528 ,  H01L23/535

Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 seem to approximately 90 seem in a chamber pressure of approximately 1 Torr to approximately 100 Torr.