公开(公告)号：US10707122B2

公开(公告)日：2020-07-07

申请号：US16140342

申请日：2018-09-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. Kesapragada ,  Kevin Moraes ,  Srinivas Guggilla ,  He Ren ,  Mehul Naik ,  David Thompson ,  Weifeng Ye ,  Yana Cheng ,  Yong Cao ,  Xianmin Tang ,  Paul F. Ma ,  Deenesh Padhi

IPC: H01L21/768 ,  H01L21/32 ,  H01L21/02 ,  H01L21/3105

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US09633839B2

公开(公告)日：2017-04-25

申请号：US14744688

申请日：2015-06-19

Applicant: APPLIED MATERIALS, INC.

Inventor： Weimin Zeng ,  Thanh X. Nguyen ,  Yana Cheng ,  Yong Cao ,  Daniel Lee Diehl ,  Srinivas Guggilla ,  Rongjun Wang ,  Xianmin Tang

IPC: H01L21/02

CPC classification number: H01L21/0234 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02266

Abstract: In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness.

公开(公告)号：US20240038833A1

公开(公告)日：2024-02-01

申请号：US18222086

申请日：2023-07-14

Applicant: Applied Materials, Inc.

Inventor： Fredrick Fishburn ,  Tomohiko Kitajima ,  Qian Fu ,  Srinivas Guggilla ,  Hang Yu ,  Jun Feng ,  Shih Chung Chen ,  Lakmal C. Kalutarage ,  Jayden Potter ,  Karthik Janakiraman ,  Deenesh Padhi ,  Yifeng Zhou ,  Yufeng Jiang ,  Sung-Kwan Kang

IPC: H10B12/00

CPC classification number: H01L28/91 ,  H01L28/92 ,  H10B12/03 ,  H10B12/30

Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where carbon is used as the removable mold material for the formation of a DRAM capacitor. A dense, high-temperature (500° C. or greater) PECVD carbon material is used as the removable mold material, e.g., the core material, instead of oxide. The carbon material can be removed by isotropic etching with exposure to radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof.

公开(公告)号：US11569257B2

公开(公告)日：2023-01-31

申请号：US16887433

申请日：2020-05-29

Applicant: Applied Materials, Inc.

Inventor： Xinhai Han ,  Deenesh Padhi ,  Er-Xuan Ping ,  Srinivas Guggilla

IPC: H01L29/792 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/1157

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

公开(公告)号：US11456173B2

公开(公告)日：2022-09-27

申请号：US16797111

申请日：2020-02-21

Applicant: Applied Materials, Inc.

Inventor： Meenakshi Gupta ,  Rui Cheng ,  Srinivas Guggilla ,  Karthik Janakiraman ,  Diwakar N. Kedlaya ,  Zubin Huang

IPC: H01L21/027 ,  H01L21/02 ,  H01L21/32

Abstract: Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.

公开(公告)号：US11101117B2

公开(公告)日：2021-08-24

申请号：US16573265

申请日：2019-09-17

Applicant: APPLIED MATERIALS, INC.

Inventor： Anantha K. Subramani ,  Hanbing Wu ,  Wei W. Wang ,  Ashish Goel ,  Srinivas Guggilla ,  Lavinia Nistor

IPC: H01J37/34 ,  C23C14/34 ,  C23C14/56 ,  H01J37/32

Abstract: Embodiments of a method and apparatus for co-sputtering multiple target materials are provided herein. In some embodiments, a process chamber including a substrate support to support a substrate; a plurality of cathodes coupled to a carrier and having a corresponding plurality of targets to be sputtered onto the substrate; and a process shield coupled to the carrier and extending between adjacent pairs of the plurality of targets.

公开(公告)号：US10109520B2

公开(公告)日：2018-10-23

申请号：US15285011

申请日：2016-10-04

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. Kesapragada ,  Kevin Moraes ,  Srinivas Guggilla ,  He Ren ,  Mehul Naik ,  David Thompson ,  Weifeng Ye ,  Yana Cheng ,  Yong Cao ,  Xianmin Tang ,  Paul F. Ma ,  Deenesh Padhi

IPC: H01L21/768 ,  H01L21/02

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.