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    MICROELECTRONIC ASSEMBLIES INCLUDING BRIDGES
    12.
    发明申请
    MICROELECTRONIC ASSEMBLIES INCLUDING BRIDGES 有权

    公开(公告)号：US20230086691A1

    公开(公告)日：2023-03-23

    申请号：US17482681

    申请日：2021-09-23

    Applicant: Intel Corporation

    Inventor： Sriram Srinivasan ,  Sanka Ganesan ,  Timothy A. Gosselin

    IPC: H01L23/538 ,  H01L21/48

    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a microelectronic subassembly including a first bridge component in a first layer, the first bridge component having a first surface and an opposing second surface, and a die in a second layer, wherein the second layer is on the first layer, and the die is electrically coupled to the second surface of the first bridge component; a package substrate having a second bridge component embedded therein, wherein the second bridge component is electrically coupled to the first surface of the first bridge component; and a microelectronic component on the second surface of the package substrate and electrically coupled to the second bridge component, wherein the microelectronic component is electrically coupled to the die via the first and second bridge components.

    PACKAGING ARCHITECTURE FOR DISAGGREGATED INTEGRATED VOLTAGE REGULATORS
    13.
    发明申请
    PACKAGING ARCHITECTURE FOR DISAGGREGATED INTEGRATED VOLTAGE REGULATORS 有权

    公开(公告)号：US20230060727A1

    公开(公告)日：2023-03-02

    申请号：US17412810

    申请日：2021-08-26

    Applicant: Intel Corporation

    Inventor： Kaladhar Radhakrishnan ,  Krishna Bharath ,  William J. Lambert ,  Adel A. Elsherbini ,  Sriram Srinivasan ,  Christopher Schaef

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

    Abstract: A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

    Differential crosstalk self-cancelation in stackable structures
    18.
    发明授权
    Differential crosstalk self-cancelation in stackable structures 有权

    公开(公告)号：US11862547B2

    公开(公告)日：2024-01-02

    申请号：US16804516

    申请日：2020-02-28

    Applicant: Intel Corporation

    Inventor： Zhichao Zhang ,  Zhe Chen ,  Srikant Nekkanty ,  Sriram Srinivasan

    IPC: H01L23/498 ,  H01L23/538 ,  H01L23/58

    CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/58

    Abstract: Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.

    ASYMMETRIC ELECTRONIC SUBSTRATE AND METHOD OF MANUFACTURE
    20.
    发明申请
    ASYMMETRIC ELECTRONIC SUBSTRATE AND METHOD OF MANUFACTURE 审中-公开

    公开(公告)号：US20200221577A1

    公开(公告)日：2020-07-09

    申请号：US16819899

    申请日：2020-03-16

    Applicant: Intel Corporation

    Inventor： Sri Chaitra Jyotsna Chavali ,  Amruthavalli Palavi Alur ,  Wei-Lun Kane Jen ,  Sriram Srinivasan

    IPC: H05K3/00 ,  H05K3/42 ,  H05K3/46 ,  H05K1/11

    Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.

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