公开(公告)号：US20180248115A1

公开(公告)日：2018-08-30

申请号：US15755446

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F10/32 ,  G11C11/16 ,  H01F41/30

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01F10/30 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/302 ,  H01F41/304 ,  H01L27/222 ,  H01L43/10 ,  H01L43/12

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include one or more electrode interface material layers disposed between a an electrode metal, such as TiN, and a seed layer of an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. The electrode interface material layers may include either or both of a Ta material layer or CoFeB material layer. In some Ta embodiments, a Ru material layer may be deposited on a TiN electrode surface, followed by the Ta material layer. In some CoFeB embodiments, a CoFeB material layer may be deposited directly on a TiN electrode surface, or a Ta material layer may be deposited on the TiN electrode surface, followed by the CoFeB material layer.

公开(公告)号：US20180166625A1

公开(公告)日：2018-06-14

申请号：US15882546

申请日：2018-01-29

Applicant: INTEL CORPORATION

Inventor： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  David L. Kencke ,  Satyarth Suri ,  Robert S. Chau

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/12

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

公开(公告)号：US09882123B2

公开(公告)日：2018-01-30

申请号：US15333017

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Uday Shah ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  Mark L. Doczy ,  Robert S. Chau

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32 ,  G11C11/18 ,  H01F10/14 ,  H01F10/16 ,  G11C11/16 ,  H01L27/22 ,  H01F10/193 ,  H01L43/02

CPC classification number: H01L43/10 ,  G11C11/161 ,  G11C11/18 ,  H01F10/14 ,  H01F10/16 ,  H01F10/1936 ,  H01F10/3236 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.

公开(公告)号：US09822470B2

公开(公告)日：2017-11-21

申请号：US13714990

申请日：2012-12-14

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Brian S. Doyle ,  Shawna M. Liff ,  Vivek K. Singh

IPC: D03D1/00 ,  H01B7/04 ,  D02G3/44 ,  D04H3/00 ,  D01D5/00 ,  D01D5/34 ,  B21C37/04 ,  B21C23/08 ,  D04H1/4266 ,  D04H1/4382

CPC classification number: D03D1/0088 ,  B21C23/08 ,  B21C37/042 ,  B21C37/047 ,  D01D5/00 ,  D01D5/34 ,  D02G3/441 ,  D04H1/4266 ,  D04H1/4382 ,  D04H3/00 ,  D10B2401/16 ,  D10B2401/18 ,  Y10T442/3057 ,  Y10T442/603

Abstract: Flexible electronically functional fibers are described that allow for the placement of electronic functionality in traditional fabrics. The fibers can be interwoven with natural fibers to produce electrically functional fabrics and devices that can retain their original appearance.

公开(公告)号：US09761724B2

公开(公告)日：2017-09-12

申请号：US15182343

申请日：2016-06-14

Applicant: Intel Corporation

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/306 ,  H01L21/84 ,  H01L29/04 ,  H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

公开(公告)号：US20170250338A1

公开(公告)日：2017-08-31

申请号：US15595868

申请日：2017-05-15

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Prashant Majhi ,  Uday Shah ,  Niloy Mukherjee ,  Elijah V. Karpov ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L45/00

CPC classification number: H01L45/122 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1675

Abstract: The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer. The present disclosure further provides a computing device. The computing device includes a motherboard, a processor mounted on the motherboard, and a communication chip fabricated on the same chip as the processor or mounted on the motherboard. The processor comprises a substrate, a first electrode, second electrode, and a RRAM layer which has a recess at the interface between the second electrode and RRAM oxide layer.

公开(公告)号：US09748371B2

公开(公告)日：2017-08-29

申请号：US15120496

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Sansaptak Dasgupta ,  Han Wui Then ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/786 ,  H01L29/24 ,  H01L21/02 ,  H01L21/8256 ,  H01L27/12 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7782 ,  H01L21/02422 ,  H01L21/02568 ,  H01L21/8256 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/0843 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78681

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US09496486B2

公开(公告)日：2016-11-15

申请号：US14812655

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Uday Shah ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Clair Webb

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L27/228 ,  H01L29/66007 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

公开(公告)号：US09478734B2

公开(公告)日：2016-10-25

申请号：US14723310

申请日：2015-05-27

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Uday Shah ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  Mark L. Doczy ,  Robert S. Chau

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32 ,  G11C11/18 ,  H01L27/22 ,  H01F10/193

CPC classification number: H01L43/10 ,  G11C11/161 ,  G11C11/18 ,  H01F10/14 ,  H01F10/16 ,  H01F10/1936 ,  H01F10/3236 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.

公开(公告)号：US09472748B2

公开(公告)日：2016-10-18

申请号：US14992601

申请日：2016-01-11

Applicant: INTEL CORPORATION

Inventor： Charles C. Kuo ,  Brian S. Doyle ,  Arijit Raychowdhury ,  Roksana Golizadeh Mojarad ,  Kaan Oguz

IPC: G11C11/00 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08 ,  H01L43/12

Abstract: Techniques are disclosed for enhancing performance of a perpendicular magnetic tunnel junction (MTJ) by implementing an additional ferromagnetic layer therein. The additional ferromagnetic layer can be implemented, for example, in or otherwise proximate either the fixed ferromagnetic layer or the free ferromagnetic layer of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is implemented with a non-magnetic spacer, wherein the thickness of the additional ferromagnetic layer and/or spacer can be adjusted to sufficiently balance the energy barrier between parallel and anti-parallel states of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is configured such that its magnetization is opposite that of the fixed ferromagnetic layer.