公开(公告)号：US20160203068A1

公开(公告)日：2016-07-14

申请号：US14998052

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F11/263 ,  G06F9/38 ,  G06F9/30 ,  G06F12/08 ,  G06F11/22

CPC classification number: G06F11/28 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/466 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/2236 ,  G06F11/25 ,  G06F11/263 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/20 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/608 ,  G06F2212/621 ,  G11C7/1072

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US20160085711A1

公开(公告)日：2016-03-24

申请号：US14869941

申请日：2015-09-29

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Robert A. Mayer ,  Stephan J. Jourdan ,  Lily Pao Looi

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4059 ,  G06F1/3206 ,  G06F1/3253 ,  G06F13/4027 ,  G06F13/4286 ,  G06F13/4295 ,  Y02B60/1228 ,  Y02B60/1235 ,  Y02D10/151

Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.

Abstract translation: 描述了用于对与处理器集成在同一裸片上的接口进行节流的方法和装置。 在一个实施例中，来自集成输入/输出集线器（例如，集成在与处理器相同的芯片上）的信号引起耦合在IIO和输入/输出（IO）设备之间的链路的节流。 还公开了其他实施例。

公开(公告)号：US10261879B2

公开(公告)日：2019-04-16

申请号：US14757919

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F15/00 ,  G06F9/00 ,  G06F9/44 ,  G06F7/00 ,  G06F11/28 ,  G06F9/46 ,  G06F9/30 ,  G06F12/0811 ,  G06F9/38 ,  G11C7/10 ,  G06F11/22 ,  G06F11/263 ,  G06F12/0897 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F11/14 ,  G06F11/25

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US10241952B2

公开(公告)日：2019-03-26

申请号：US14869941

申请日：2015-09-29

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Robert A. Mayer ,  Stephan J. Jourdan ,  Lily Pao Looi

IPC: G06F13/40 ,  G06F1/3234 ,  G06F1/3206 ,  G06F13/42

Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.

公开(公告)号：US20170235580A1

公开(公告)日：2017-08-17

申请号：US15586930

申请日：2017-05-04

Applicant: Intel Corporation

Inventor： Laura A. Knauth ,  Ravi Rajwar ,  Peggy J. Irelan ,  Konrad K. Lai ,  Martin G. Dixon

IPC: G06F9/38 ,  G06F9/46 ,  G06F12/084 ,  G06F13/42 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3861 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/467 ,  G06F9/528 ,  G06F11/1407 ,  G06F11/1469 ,  G06F11/3048 ,  G06F11/3051 ,  G06F11/348 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1673 ,  G06F13/4282 ,  G06F15/80 ,  G06F2201/84 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/62 ,  G06F2213/0026

Abstract: An example system for speculative execution event counter checkpointing and restoring may include a plurality of processors, a first interconnect to couple two or more of the plurality of processors, a second interconnect to couple one or more of the plurality of processors to one or more other system components, and a system memory coupled to one or more of the processors. At least one processor of the plurality of processors may include: a plurality of symmetric cores, at least one of the symmetric cores to simultaneously process a plurality of threads and to perform out-of-order instruction processing for the plurality of threads; at least one shared cache circuit to be shared among two or more the of symmetric cores; and event counter circuitry comprising: a plurality of event counters including programmable event counters and fixed event counters; one or more configuration registers to store configuration data to specify an event type to be counted by the programmable event counters, wherein at least one of the one or more configuration registers is to store configuration data for a plurality of the programmable event counters. The processor may further include transactional memory circuitry to process transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to indicate a start of a transactional execution region of a program, a transaction end instruction to indicate an end of the transactional execution region, and a transaction abort instruction to abort processing of the transactional execution region. The processor may further include transaction checkpoint circuitry to store a processor state at the start of the transactional execution region of the program, the processor state including values of one or more of the event counters. The processor may further include lock elision circuitry to cause critical sections of the program to execute as transactions on multiple threads without acquiring a lock, the lock elision circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.

公开(公告)号：US20160232041A1

公开(公告)日：2016-08-11

申请号：US15131099

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Peter Lachner ,  Laura A. Knauth ,  Konrad K. Lai

IPC: G06F9/52 ,  G06F11/14 ,  G06F9/38

CPC classification number: G06F9/528 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/3476 ,  G06F11/3636

Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行单元和至少一个最后一个分支记录（LBR）寄存器，用于存储在程序执行期间所采取的分支的地址信息。 该寄存器还可以存储事务指示符以指示在事务存储器（TM）事务期间是否采取了分支。 该寄存器可以进一步存储中止指示符以指示分支是否由事务中止引起。 描述和要求保护其他实施例。

公开(公告)号：US09372764B2

公开(公告)日：2016-06-21

申请号：US14555104

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Laura A. Knauth ,  Ravi Rajwar ,  Konrad K. Lai ,  Martin G. Dixon ,  Peggy Irelan

IPC: G06F11/14 ,  G06F9/46 ,  G06F9/38 ,  G06F11/34

CPC classification number: G06F11/1469 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/466 ,  G06F11/1451 ,  G06F11/3466 ,  G06F2201/82 ,  G06F2201/84 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88

Abstract: Event counter checkpointing and restoring is disclosed. In one implementation, a processor includes a first event counter to count events that occur during execution within the processor, event counter checkpoint logic, communicably coupled with the first event counter, to store, prior to a transactional execution of the processor, a value of the first event counter, a second event counter to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is aborted, event count restore logic to restore the first event counter to the stored value after the transactional execution is aborted, and tuning logic to determine, in response to aborting of the transactional execution, a number of the events that occurred during the transactional execution based on the stored value of the first event counter and a value of the second event counter.

Abstract translation: 公开了事件计数器检查点和恢复。 在一个实现中，处理器包括第一事件计数器，用于计数在处理器内执行期间发生的事件，与第一事件计数器通信地耦合的事件计数器检查点逻辑，以在处理器的事务执行之前存储值 第一事件计数器，在事务执行之前和期间对事件进行计数的第二事件计数器，其中第二事件计数器在事务执行中止之后增加而不重置，事件计数恢复逻辑将第一事件计数器还原到所存储的 以及调整逻辑，以响应于事务执行中止，确定在事务执行期间基于第一事件计数器的存储值和第二事件计数器的值发生的事件的数量 事件柜台

公开(公告)号：US09354878B2

公开(公告)日：2016-05-31

申请号：US13918147

申请日：2013-06-14

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Peter Lachner ,  Laura A. Knauth ,  Konrad K. Lai

IPC: G06F9/30 ,  G06F11/34 ,  G06F11/36 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/528 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/3476 ,  G06F11/3636

Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行单元和至少一个最后一个分支记录（LBR）寄存器，用于存储在程序执行期间所采取的分支的地址信息。 该寄存器还可以存储事务指示符以指示在事务存储器（TM）事务期间是否采取了分支。 该寄存器可以进一步存储中止指示符以指示分支是否由事务中止引起。 描述和要求保护其他实施例。

公开(公告)号：US20150089286A1

公开(公告)日：2015-03-26

申请号：US14555104

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Laura A. Knauth ,  Ravi Rajwar ,  Konrad K. Lai ,  Martin G. Dixon ,  Peggy Irelan

IPC: G06F11/14

CPC classification number: G06F11/1469 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/466 ,  G06F11/1451 ,  G06F11/3466 ,  G06F2201/82 ,  G06F2201/84 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88

Abstract: Event counter checkpointing and restoring is disclosed. In one implementation, a processor includes a first event counter to count events that occur during execution within the processor, event counter checkpoint logic, communicably coupled with the first event counter, to store, prior to a transactional execution of the processor, a value of the first event counter, a second event counter to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is aborted, event count restore logic to restore the first event counter to the stored value after the transactional execution is aborted, and tuning logic to determine, in response to aborting of the transactional execution, a number of the events that occurred during the transactional execution based on the stored value of the first event counter and a value of the second event counter.

Abstract translation: 公开了事件计数器检查点和恢复。 在一个实现中，处理器包括第一事件计数器，用于计数在处理器内执行期间发生的事件，与第一事件计数器通信地耦合的事件计数器检查点逻辑，以在处理器的事务执行之前存储值 第一事件计数器，在事务执行之前和期间对事件进行计数的第二事件计数器，其中第二事件计数器在事务执行中止之后增加而不重置，事件计数恢复逻辑将第一事件计数器还原到所存储的 以及调整逻辑，以响应于事务执行中止，确定在事务执行期间基于第一事件计数器的存储值和第二事件计数器的值发生的事件的数量 事件柜台

公开(公告)号：US10409612B2

公开(公告)日：2019-09-10

申请号：US14998249

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  Ravi Rajwar ,  Konrad K. Lai ,  Robert S. Chappell ,  Rajesh S. Parthasarathy ,  Alexandre J. Farcy ,  Ilhyun Kim ,  Prakash Math ,  Matthew Merten ,  Vijaykumar Kadgi

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/16 ,  G06F13/40 ,  G06F12/084 ,  G06F12/0895 ,  G06F13/42 ,  G06F12/0831 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/1027 ,  G06F9/46 ,  G06F12/0815 ,  G06F12/1045 ,  G06F12/0806

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.