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    WIRING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
    14.
    发明申请
    WIRING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 有权
    配线基板及其制造方法

    公开(公告)号：US20160338195A1

    公开(公告)日：2016-11-17

    申请号：US15153884

    申请日：2016-05-13

    Applicant: IBIDEN CO. LTD.

    Inventor： Kosuke IKEDA

    IPC: H05K1/02 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11 ,  H05K1/03

    CPC classification number: H05K1/0298 ,  H05K1/0204 ,  H05K1/0373 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4038 ,  H05K3/4652 ,  H05K3/4661 ,  H05K3/4673 ,  H05K3/4697 ,  H05K2201/0183 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/10416

    Abstract: A wiring substrate includes a core substrate, and a build-up layer including conductor layers and insulating layers alternately laminated on the substrate and via conductors formed in the insulating layers, each insulating layer having a coating layer and a support layer stacked on the coating layer such that the support layer has surface on which a conductor layer is laminated and the coating layer is covering a conductor layer, each via conductor connecting two conductor layers through an insulating layer. The coating layer has a thickness greater than that of the support layer and includes inorganic filler at content rate of 65 to 85% by mass, and the support layer includes inorganic filler at different content rate such that thermal expansion coefficient of the coating layer is smaller than that of the support layer and the coefficients of the coating and support layers have difference of 30 ppm/° C. or less.

    Abstract translation: 布线基板包括芯基板和包括导体层和绝缘层的堆积层，交替层叠在基板上，并且经由形成在绝缘层中的导体，每个绝缘层具有层叠在涂层上的涂层和支撑层 使得支撑层具有其上层叠导体层的表面，并且涂层覆盖导体层，每个通孔导体通过绝缘层连接两个导体层。 涂层的厚度大于支撑层的厚度，包含含量为65〜85质量％的无机填料，支承层包含不同含量的无机填料，使得涂层的热膨胀系数较小 与支撑层的系数相比，涂层和支撑层的系数差为30ppm /℃或更低。

    COMPENSATING FOR INTRA-PAIR SKEW IN DIFFERENTIAL SIGNALING
    16.
    发明申请
    COMPENSATING FOR INTRA-PAIR SKEW IN DIFFERENTIAL SIGNALING 有权
    对差异信号中的对角线进行补偿

    公开(公告)号：US20150327358A1

    公开(公告)日：2015-11-12

    申请号：US14275604

    申请日：2014-05-12

    Applicant: FUJITSU LIMITED

    Inventor： Yasuo HIDAKA

    IPC: H05K1/02 ,  H05K3/00 ,  H05K3/46 ,  H05K1/03

    CPC classification number: H05K1/0245 ,  H01P3/08 ,  H05K1/024 ,  H05K1/0248 ,  H05K1/0313 ,  H05K1/0366 ,  H05K1/038 ,  H05K3/0091 ,  H05K3/10 ,  H05K3/4644 ,  H05K2201/0183 ,  H05K2201/07 ,  H05K2203/0195

    Abstract: A circuit may be configured to reduce electrical signal degradation. The circuit may include a first trace and a second trace that may be broadside coupled between a first ground plane and a second ground plane. The first and second traces may be configured to carry first and second signals, respectively, of a differential signal. The circuit may also include a first dielectric material disposed between the first trace and the second trace. Further, the circuit may include a second dielectric material disposed between the first trace and the first ground plane and disposed between the second trace and the second ground plane. A difference between a first dielectric constant of the first dielectric material and a second dielectric constant of the second dielectric material may suppress a mode conversion of the differential signal from a differential mode to a common mode.

    Abstract translation: 电路可以被配置为减少电信号衰减。 电路可以包括可以在第一接地平面和第二接地平面之间的宽边耦合的第一迹线和第二迹线。 第一和第二迹线可以被配置为分别携带差分信号的第一和第二信号。 电路还可以包括设置在第一迹线和第二迹线之间的第一介电材料。 此外，电路可以包括设置在第一迹线和第一接地平面之间并且设置在第二迹线和第二接地平面之间的第二介电材料。 第一介电材料的第一介电常数和第二介电材料的第二介电常数之间的差异可以抑制差分信号从差分模式到共模的模式转换。

    CIRCUIT CARRIER BOARD
    17.
    发明公开
    CIRCUIT CARRIER BOARD 审中-公开

    公开(公告)号：US20240292517A1

    公开(公告)日：2024-08-29

    申请号：US18481097

    申请日：2023-10-04

    Applicant: Asia Pacific Microsystems, Inc.

    Inventor： Jer-Wei HSIEH ,  Hung-Lin YIN

    IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18

    CPC classification number: H05K1/0233 ,  H05K1/024 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/184 ,  H05K2201/0183 ,  H05K2201/0206 ,  H05K2201/083

    Abstract: A carrier board includes a substrate having a first substrate surface, a second substrate surface, and a substrate hole that penetrates the first substrate surface and the second substrate surface; a magnet sheath disposed in the substrate hole to cover a hole boundary of the substrate hole, and including a first magnetic surface, a second magnetic surface, and an inner periphery that interconnects the first magnetic surface and the second magnetic surface; a first dielectric isolation layer and a second dielectric isolation layer respectively having outer surfaces facing away from the substrate; and a conductive metal layer covering the inner periphery of the magnet sheath and extending to overlie the outer surfaces of the first dielectric isolation layer and the second dielectric isolation layer.

    UWB BANDPASS FILTER
    18.
    发明公开
    UWB BANDPASS FILTER 审中-公开

    公开(公告)号：US20240120630A1

    公开(公告)日：2024-04-11

    申请号：US18542601

    申请日：2023-12-16

    Applicant: HELLA GmbH & Co. KGaA

    Inventor： Joerg SCHRAPE ,  Belal Abu SUHEIL

    IPC: H01P1/203 ,  H05K1/02

    CPC classification number: H01P1/2039 ,  H05K1/024 ,  H05K1/0259 ,  H05K2201/0183

    Abstract: A UWB band pass filter that is formed by a circuit board. The circuit board includes a first dielectric layer made of a dielectric substrate, a filter structure made of electrically conductive material, on a first side of the first dielectric layer, a first ground layer made of electrically conductive material, on a second side of the first dielectric layer. The filter structure has an input terminal and an output terminal between which a line extends that includes multiple first line sections and second line sections, and wherein the filter structure has multiple stubs that are situated between the first line sections and that branch off from the second line sections. The first line sections and the stubs are situated in parallel. The longitudinal line of the middle first line sections is inserted, from which two open stubs that are rotationally symmetrical about the middle first line sections branch off.

    Circuit Assemblies And Related Methods
    19.
    发明申请
    Circuit Assemblies And Related Methods 审中-公开

    公开(公告)号：US20180295713A1

    公开(公告)日：2018-10-11

    申请号：US16003626

    申请日：2018-06-08

    Applicant: Laird Technologies, Inc.

    Inventor： John SONG ,  George William RHYNE

    IPC: H05K1/02 ,  H05K9/00 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30

    CPC classification number: H05K1/0216 ,  H05K1/0296 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K9/0024 ,  H05K2201/0183 ,  H05K2201/0715 ,  H05K2201/0999 ,  H05K2201/10371

    Abstract: In exemplary embodiments, a circuit assembly may be provided on and/or supported by an electrically conductive structure, such as a board level shield, a midplate, a bracket, a precision metal part, etc. For example, a circuit assembly may be provided on and/or supported by an outer top surface of a board level shield. In an exemplary embodiment, an assembly generally includes an electrically conductive structure configured for a first functionality in the electronic device. An electrically nonconductive material is on at least part of the electrically conductive structure. First electrical component(s) are at least partly on the electrically nonconductive layer and configured to define at least a portion of a circuit assembly for electrical connection with one or more second electrical components of the electronic device. The electrically conductive structure may thus be configured for a second functionality in the electronic device.

    Circuit assemblies and related methods
    20.
    发明授权
    Circuit assemblies and related methods 有权

    公开(公告)号：US09999122B2

    公开(公告)日：2018-06-12

    申请号：US15783191

    申请日：2017-10-13

    Applicant: Laird Technologies, Inc.

    Inventor： John Song ,  George William Rhyne

    IPC: H05K9/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30 ,  H05K1/14

    CPC classification number: H05K1/0216 ,  H05K1/0296 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K9/0024 ,  H05K2201/0183 ,  H05K2201/0715 ,  H05K2201/0999 ,  H05K2201/10371

    Abstract: In exemplary embodiments, a circuit assembly may be provided on and/or supported by an electrically conductive structure, such as a board level shield, a midplate, a bracket, a precision metal part, etc. For example, a circuit assembly may be provided on and/or supported by an outer top surface of a board level shield. In an exemplary embodiment, an assembly generally includes an electrically conductive structure configured for a first functionality in the electronic device. An electrically nonconductive layer is on at least part of the electrically conductive structure. First electrical component(s) are at least partly on the electrically nonconductive layer and configured to define at least a portion of a circuit assembly for electrical connection with one or more second electrical components of the electronic device. The electrically conductive structure may thus be configured for a second functionality in the electronic device.

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