公开(公告)号：US09590154B2

公开(公告)日：2017-03-07

申请号：US14459621

申请日：2014-08-14

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yasuyoshi Horikawa

IPC: H01L33/60 ,  H01L33/62 ,  H05K1/02 ,  H05K1/18 ,  H01L25/16 ,  H05K1/05

CPC classification number: H01L33/60 ,  H01L24/45 ,  H01L25/167 ,  H01L33/62 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0274 ,  H05K1/056 ,  H05K1/187 ,  H05K1/188 ,  H05K2201/0376 ,  H05K2201/10106 ,  H05K2201/10174 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wiring substrate includes an insulation layer, separated wires formed on a first surface of the insulation layer, a first plating layer formed on a first surface of each of the wires, a reflection layer including a first opening that exposes at least a portion of the first plating layer as a connection pad, and an electronic component mounted on a second surface of each of the wires, which is located on an opposite side of the first surface of each of the wires. The electronic component is embedded in the insulation layer.

Abstract translation: 布线基板包括绝缘层，形成在绝缘层的第一表面上的分离线，形成在每条导线的第一表面上的第一镀层，包括第一开口的反射层，该第一开口暴露至少一部分 第一电镀层作为连接焊盘，以及电子部件，其安装在每个电线的第二表面上，该电子部件位于每个电线的第一表面的相对侧上。 电子部件嵌入绝缘层。

公开(公告)号：US20170033037A1

公开(公告)日：2017-02-02

申请号：US15293883

申请日：2016-10-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Ching Ho ,  Ying-Chou Tsai ,  Sheng-Che Huang

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/81193 ,  H05K3/064 ,  H05K3/205 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4682 ,  H05K2201/0376 ,  Y02P70/613 ,  Y10T29/49158

Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

Abstract translation: 公开了一种封装基板，包括：介电层; 电介质层，其中所述电路层嵌入并暴露于所述电介质层的表面，其中所述电路层具有多个导电焊盘; 以及形成在所述导电焊盘上并突出在所述电介质层的表面上方的多个导电凸块。 这样，当通过多个导电元件将电子元件设置在导电焊盘上时，导电元件可以与导电凸块的顶表面和侧表面接触，从而增加导电元件与导电元件之间的接触面积 导电焊盘，从而加强导电元件和导电焊盘之间的接合，并防止导电元件与导电焊盘分层。

公开(公告)号：US09532462B2

公开(公告)日：2016-12-27

申请号：US13512271

申请日：2010-11-25

Applicant: Yeong Uk Seo ,  Sung Woon Yoon ,  Jin Su Kim ,  Myoung Hwa Nam ,  Sang Myung Lee ,  Chi Hee Ahn

Inventor： Yeong Uk Seo ,  Sung Woon Yoon ,  Jin Su Kim ,  Myoung Hwa Nam ,  Sang Myung Lee ,  Chi Hee Ahn

IPC: H05K1/00 ,  H05K1/09 ,  H05K3/10 ,  H05K3/20 ,  H05K1/02 ,  H05K1/03 ,  H05K3/02

CPC classification number: H05K3/101 ,  H05K1/02 ,  H05K1/0353 ,  H05K1/092 ,  H05K3/02 ,  H05K3/108 ,  H05K3/20 ,  H05K2201/0376 ,  H05K2203/0278

Abstract: The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.

Abstract translation: 本发明提供一种印刷电路板的结构及其制造方法。 该方法包括：（a）在形成种子层的绝缘层上形成电路图形; （b）通过压制方法将电路图案嵌入绝缘层; 和（c）去除种子层。 根据本发明，可以通过在绝缘层上直接形成电路图案而形成不发生取向问题的精细图案，并且通过执行将突出电路嵌入绝缘层中的工艺可以提高形成的精细图案的可靠性。 此外，通过在去除种子层的蚀刻工艺期间，通过在电路层上过度蚀刻比低于绝缘层的表面的电路层，由于相邻电路之间的离子迁移而发生劣质电路的可能性可能会降低。

公开(公告)号：US20160353570A1

公开(公告)日：2016-12-01

申请号：US15136231

申请日：2016-04-22

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sung Chul LEE

IPC: H05K1/03 ,  C08K3/36 ,  H05K3/10 ,  C08K3/26 ,  C08J5/18 ,  C08K7/00 ,  C08K3/40

CPC classification number: H05K1/0373 ,  C08K3/013 ,  C08K3/26 ,  C08K3/36 ,  C08K3/40 ,  C08K7/00 ,  C08K2003/265 ,  C08K2201/016 ,  H05K2201/0209 ,  H05K2201/0248 ,  H05K2201/0376 ,  C08L63/00

Abstract: A resin composition for packaging, an insulating film and a printed circuit board manufactured with the resin composition, and a method of manufacturing a printed circuit board with the resin composition are provided. The resin composition for packaging includes an epoxy resin, and inorganic filler particles dispersed in the epoxy resin, and an aspect ratio of the inorganic filler particles is 1.0 or more and 3.0 or less.

Abstract translation: 提供了一种用于包装的树脂组合物，绝缘膜和用树脂组合物制造的印刷电路板，以及制造具有树脂组合物的印刷电路板的方法。 用于包装的树脂组合物包括环氧树脂和分散在环氧树脂中的无机填料颗粒，无机填料颗粒的纵横比为1.0以上至3.0以下。

公开(公告)号：US09508634B2

公开(公告)日：2016-11-29

申请号：US15133244

申请日：2016-04-20

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu

IPC: H05K7/10 ,  H05K7/12 ,  H01L23/495 ,  H01L21/768 ,  H05K1/03 ,  H05K3/18 ,  H05K3/40 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10 ,  H05K3/46

CPC classification number: H01L23/49586 ,  H01L21/4828 ,  H01L21/76823 ,  H01L21/76825 ,  H01L23/13 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49558 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2924/181 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A package structure includes a lead frame, a selective-electroplating epoxy compound, conductive vias and a patterned circuit layer. The lead frame includes a metal stud array having metal studs. The selective-electroplating epoxy compound covers the metal stud array. The selective-electroplating epoxy compound includes non-conductive metal complex. The conductive vias are directly embedded in the selective electroplating epoxy compound to be respectively connected to the metal studs and extended to a top surface of the selective-electroplating epoxy compound. Each of the conductive vias includes a lower segment connected to the corresponding metal stud and an upper segment connected to the lower segment and extended to the top surface, and a smallest diameter of the upper segment is greater than a largest diameter of the lower segment. The patterned circuit layer is directly disposed on the top surface and electrically connected to the conductive vias.

Abstract translation: 封装结构包括引线框，选择性电镀环氧化合物，导电通孔和图案化电路层。 引线框架包括具有金属螺柱的金属螺柱阵列。 选择性电镀环氧化合物覆盖金属螺柱阵列。 选择性电镀环氧化合物包括非导电金属络合物。 导电通孔直接嵌入选择性电镀环氧化合物中，以分别连接到金属螺柱并延伸到选择性电镀环氧化合物的顶表面。 每个导电通孔包括连接到相应的金属螺柱的下部段和连接到下部段并延伸到顶部表面的上段，并且上段的最小直径大于下段的最大直径。 图案化电路层直接设置在顶表面上并电连接到导电通孔。

公开(公告)号：US09465501B2

公开(公告)日：2016-10-11

申请号：US14023757

申请日：2013-09-11

Applicant: Ronald Steven Cok

Inventor： Ronald Steven Cok

IPC: H05K3/40 ,  H05K3/46 ,  G06F3/047 ,  G06F3/044 ,  H05K1/02 ,  H05K1/11 ,  H05K1/09

CPC classification number: G06F3/047 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04112 ,  H01L29/413 ,  H01L33/42 ,  H01L51/5215 ,  H05K1/0289 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/117 ,  H05K3/465 ,  H05K3/4664 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09845 ,  Y10T29/49155

Abstract: A method of making a multi-layer micro-wire structure includes providing a substrate having a substrate edge and first and second layers formed over the substrate. One or more micro-channels are imprinted in each of the first and second layers and first and second micro-wires located in the imprinted micro-channels, the micro-wires forming at least a portion of an exposed connection pad in each layer. The second layer edge is farther from the substrate edge than the first layer edge for at least a portion of the second layer edge so that the first connection pads are exposed through the second layer.

Abstract translation: 制造多层微线结构的方法包括提供具有衬底边缘的衬底和形成在衬底上的第一和第二层。 一个或多个微通道被印刷在第一和第二层中的每一个以及位于压印的微通道中的第一和第二微细线中，微线形成每个层中暴露的连接焊盘的至少一部分。 对于第二层边缘的至少一部分，第二层边缘比距第一层边缘更远离基板边缘，使得第一连接焊盘通过第二层曝光。

公开(公告)号：US09445504B2

公开(公告)日：2016-09-13

申请号：US14004557

申请日：2012-04-19

Applicant: Jae Wook Kang ,  Do Geun Kim ,  Jong Kuk Kim ,  Sung Hun Jung ,  Myungkwan Song ,  Dae Sung You ,  Chang Soo Kim ,  Kee Seok Nam

Inventor： Jae Wook Kang ,  Do Geun Kim ,  Jong Kuk Kim ,  Sung Hun Jung ,  Myungkwan Song ,  Dae Sung You ,  Chang Soo Kim ,  Kee Seok Nam

IPC: H05K3/00 ,  H05K3/10 ,  H05K1/02 ,  H05K3/20 ,  H05K1/03 ,  H05K3/24

CPC classification number: H05K3/0017 ,  H05K1/02 ,  H05K1/0393 ,  H05K3/10 ,  H05K3/207 ,  H05K3/246 ,  H05K2201/0376 ,  Y10T29/49156

Abstract: Disclosed are a method of manufacturing a metal wiring buried flexible substrate and a flexible substrate manufactured by the same. The method includes coating a sacrificial layer including a polymer soluble in water or an organic solvent, or a photodegradable polymer on a substrate (Step 1), forming a metal wiring on the sacrificial layer in Step 1 (Step 2), forming a metal wiring buried polymer layer by coating a curable polymer on the sacrificial layer including the metal wiring formed thereon in Step 2 and curing (Step 3) and separating the polymer layer in Step 3 from the substrate in Step 1 by removing through dissolving in the water or the organic solvent or photodegrading only the sacrificial layer present between the substrate in Step 1 and the polymer layer in Step 3 (Step 4).

Abstract translation: 公开了一种制造金属布线埋地柔性基板和由其制造的柔性基板的方法。 该方法包括将包含可溶于水或有机溶剂的聚合物或光可降解聚合物的牺牲层涂覆在基材上（步骤1），在步骤1（步骤2）中在牺牲层上形成金属布线，形成金属布线 通过在步骤2中包括在其上形成的金属布线的牺牲层上涂覆可固化聚合物并固化（步骤3），并且在步骤1中通过溶解在水中除去步骤3中的聚合物层和步骤1中的基底， 有机溶剂或光降解步骤1中的基板与步骤3中的聚合物层之间存在的牺牲层（步骤4）。

公开(公告)号：US20160255717A1

公开(公告)日：2016-09-01

申请号：US15052009

申请日：2016-02-24

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki FURUTANI ,  Yasushi INAGAKI ,  Shunsuke SAKAI

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0271 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/007 ,  H05K3/4658 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/10734

Abstract: A multilayer wiring board includes wiring bodies each including an insulating layer, a conductor layer embedded in the insulating layer and having exposed surface on first surface of the insulating layer, and a conductor post formed on embedded surface of the conductor layer on the opposite side and having end surface on second surface of the insulating layer. The bodies include first and second bodies forming outermost layers on the opposite sides, the exposed surface is recessed from the first surface of the insulating layer in the first body, the end surface is recessed from the second surface in the second body in recess amount greater than that of the exposed surface in the first body, the post of the first body has the exposed surface bonded to the conductor layer of an adjacent body, the second body has the conductor layer bonded to the post of an adjacent body.

Abstract translation: 多层布线基板包括布线体，每个布线体包括绝缘层，埋在绝缘层中的导体层，并且在绝缘层的第一表面上具有暴露表面;导体柱，形成在导体层的相对侧的嵌入表面上， 在绝缘层的第二表面上具有端面。 这些主体包括在相对侧上形成最外层的第一和第二主体，暴露的表面从第一主体中的绝缘层的第一表面凹陷，端面从第二主体中的第二表面凹入更大的凹陷量 比第一主体中的暴露表面的第一主体的柱具有暴露的表面结合到相邻体的导体层，第二主体具有结合到相邻体的柱的导体层。

公开(公告)号：US09408313B2

公开(公告)日：2016-08-02

申请号：US14174858

申请日：2014-02-07

Applicant: Unimicron Technology Corp.

Inventor： Chun-Ting Lin ,  Ying-Chih Chan

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/06

CPC classification number: H05K3/4007 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81385 ,  H05K3/062 ,  H05K2201/0367 ,  H05K2201/0376 ,  Y10T29/49156 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A packaging substrate is provided, including a substrate body and conductive pillars. The substrate body has a first surface and a second surface opposite to the first surface. The first surface has a plurality of first conductive pads, and the second surface has a die attach area and a peripheral area surrounding the die attach area. The die attach area has a plurality of second conductive pads embedded therein, wherein top surfaces of the second conductive pads are exposed from the second surface, and the die attach area of the second surface is fully exposed. The conductive pillars are correspondingly disposed on the second conductive pads and have first ends and opposite second ends. The first ends are closer than the second ends from the second conductive pads, and the first ends have a width bigger than a width of the second ends. A fabricating method thereof is also provided.

Abstract translation: 提供了一种包装基板，包括基体和导电支柱。 基板主体具有与第一表面相对的第一表面和第二表面。 第一表面具有多个第一导电焊盘，第二表面具有管芯附着区域和围绕管芯附着区域的周边区域。 管芯附着区域具有嵌入其中的多个第二导电焊盘，其中第二导电焊盘的顶表面从第二表面露出，并且第二表面的管芯附着区域被完全暴露。 导电柱相应地设置在第二导电焊盘上并且具有第一端和相对的第二端。 第一端比第二导电焊盘更靠近第二端，并且第一端的宽度大于第二端的宽度。 还提供了其制造方法。

公开(公告)号：US09370110B2

公开(公告)日：2016-06-14

申请号：US14225682

申请日：2014-03-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/10 ,  H05K3/28 ,  H05K3/34

CPC classification number: H05K3/4611 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/421 ,  H05K3/4658 ,  H05K2201/0376 ,  H05K2203/06 ,  H05K2203/0723 ,  H05K2203/143

Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.

Abstract translation: 制造多层基板结构的方法包括预处理，压制和后处理的步骤。 设置有电路图案层的承载板被压靠在塑料片上。 通过钻孔和填充塑料片的下表面形成夹层连接垫。 将载板，塑料片，另一塑料片和具有电路图案层的另一载体板压在一起，然后钻孔/填充以形成多层堆叠结构，使得两个电路图案层间接地并电连接到中间层 连接垫。 因此，可以通过使用比对准公差宽的层间连接焊盘来克服由于对准公差引起的问题，并且堆叠各个具有更细的线和更小间距的电路层。