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11.发明授权公开(公告)号：US09900970B2
公开(公告)日：2018-02-20
申请号：US14975951
申请日：2015-12-21
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
CPC classification number: H05F3/02 , G01R1/07378 , G01R1/36 , H01L2924/15174 , H01L2924/15311 , H02H9/046 , H05K1/11 , H05K1/181 , H05K2201/07 , H05K2201/10734
Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
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公开(公告)号：US09774070B2
公开(公告)日：2017-09-26
申请号：US14537059
申请日：2014-11-10
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Nobuo Ikemoto , Yuki Wakabayashi , Shigeru Tago
IPC: H01P3/08 , H01P11/00 , H05K1/02 , H05K1/11 , H05K1/14 , H05K3/36 , H01R12/62 , H05K3/00 , H05K3/46 , H01R103/00 , H01R24/50
CPC classification number: H01P3/082 , H01P3/08 , H01P11/003 , H01R12/62 , H01R24/50 , H01R2103/00 , H05K1/0219 , H05K1/0225 , H05K1/024 , H05K1/0242 , H05K1/0253 , H05K1/115 , H05K1/118 , H05K1/147 , H05K3/0052 , H05K3/363 , H05K3/4623 , H05K3/4632 , H05K2201/07 , H05K2201/09154 , H05K2201/0919 , H05K2201/09481 , H05K2201/09527 , H05K2201/096 , H05K2201/09618 , H05K2201/097 , H05K2201/09845 , H05K2201/10037 , H05K2201/10204 , Y10T29/49016
Abstract: In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.
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公开(公告)号：US09565777B1
公开(公告)日：2017-02-07
申请号：US14970165
申请日：2015-12-15
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Brian M. Erwin
IPC: H05K3/46 , H05K1/09 , H05K1/11 , H05K3/06 , C25D11/04 , C25D11/16 , H05K1/00 , H05K1/16 , H05K1/03
CPC classification number: H05K1/0275 , B05D3/102 , B41N1/083 , C23C22/66 , C23C22/76 , C23C22/78 , C25D11/04 , C25D11/045 , C25D11/16 , H01L23/57 , H05K1/00 , H05K1/0306 , H05K1/0393 , H05K1/09 , H05K1/115 , H05K1/16 , H05K3/06 , H05K3/28 , H05K3/4038 , H05K3/4602 , H05K3/4644 , H05K3/4682 , H05K3/4697 , H05K2201/07 , H05K2201/09681 , H05K2203/0307 , H05K2203/0315 , H05K2203/033 , H05K2203/0369 , H05K2203/0392 , H05K2203/0733 , H05K2203/1142
Abstract: A method of making a security mesh comprises forming on a conductive substrate an alumina film having through-holes in which metal, e.g., copper, through-wires are formed. First surface wires are formed on one surface of the alumina film and second surface wires are formed on the second, opposite surface of the alumina film in order to connect selected through-wires into a continuous undulating electrical circuit embedded within the alumina film. The security mesh product comprises an alumina film having a continuous undulating electrical circuit comprising copper or other conductive metal extending therethrough. A stacked security mesh comprises two or more of the mesh products being stacked one above the other.
Abstract translation: 制造安全网的方法包括在导电基板上形成具有通孔的氧化铝膜，其中形成有例如铜的通孔。 第一表面线形成在氧化铝膜的一个表面上，并且第二表面线形成在氧化铝膜的第二相对表面上，以便将所选择的通孔连接到嵌入在氧化铝膜内的连续起伏的电路中。 安全网产品包括氧化铝膜，其具有包括铜或延伸穿过其中的其它导电金属的连续波形电路。 堆叠的安全网格包括两个或多个网格产品，一个彼此堆叠。
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公开(公告)号：US20160150639A1
公开(公告)日：2016-05-26
申请号：US14947065
申请日：2015-11-20
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, JR. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers and connecting to respective signal traces on a breakout layer of the routing layers; an antipad of a first type around and between the first and second signal vias in one or more of the attachment layers; and antipads of a second type around the first and second signal vias in at least one routing layer adjacent to the breakout layer.
Abstract translation: 印刷电路板包括多个层，包括附着层和布线层; 形成差分信号对的第一和第二信号通孔，第一和第二信号通孔延伸穿过连接层并连接到路由层的突围层上的各个信号迹线; 围绕一个或多个附着层中的第一和第二信号通孔之间和第一信号通路之间的第一类型的止动件; 以及围绕与突出层相邻的至少一个路由层中的第一和第二信号通孔周围的第二类型的反码器。
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公开(公告)号：US20170280557A1
公开(公告)日：2017-09-28
申请号：US15408672
申请日：2017-01-18
Applicant: Silicon Motion, Inc.
Inventor： I-Hung HUANG
CPC classification number: H05K1/0271 , G01R1/0416 , G01R31/003 , G01R31/44 , H05K1/0298 , H05K1/111 , H05K1/115 , H05K1/18 , H05K3/28 , H05K2201/07 , H05K2201/09909 , H05K2201/09972
Abstract: The present invention provides a printed circuit board assembly including a substrate having a plurality of conductive layers vertically sandwiched between a first cap-insulation layer and a second cap-insulation layer. The substrate has a first part, a second part and a third part. For protecting the conductive layers from moisture, each of the areas of the conductive layers corresponding to the second part is smaller than the area of the first cap-insulation layer corresponding to the second part for at least a first predetermined percentage, and each of the areas of the conductive layers corresponding to the second part is smaller than the area of the second cap-insulation layer corresponding to the second part for at least the first predetermined percentage.
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Patent Agency Ranking
公开(公告)号：US09692180B2
公开(公告)日：2017-06-27
申请号：US14948519
申请日：2015-11-23
Applicant: CommScope Technologies LLC
Inventor： Steven Richard Bopp , Neil Ktul Nay
IPC: H01R13/6466 , H01R13/6469 , H01R24/64 , H01R13/6461 , H05K1/02 , H05K1/11 , H01R107/00
CPC classification number: H01R13/6466 , H01R13/6461 , H01R13/6469 , H01R24/64 , H01R2107/00 , H05K1/0228 , H05K1/0239 , H05K1/11 , H05K2201/07 , H05K2201/10189
Abstract: An electrical connector that includes a circuit board having a board substrate that has opposite board surfaces and a thickness measured along an orientation axis that extends between the opposite board surfaces. The circuit board has associated pairs of input and output terminals and signal traces that electrically connect the associated pairs of input and output terminals. The input and output terminals being configured to communicatively coupled to mating and cable conductors, respectively. Each associated pair of input and output terminals is electrically connected through a corresponding signal trace that has a conductive path extending along the board substrate between the corresponding input and output terminals. At least two signal traces form a broadside-coupling region in which the conductive paths of the at least two signal traces are stacked along the orientation axis and spaced apart through the thickness and extend parallel to each other for a crosstalk-reducing distance.
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公开(公告)号：US09655231B2
公开(公告)日：2017-05-16
申请号：US14275604
申请日：2014-05-12
Applicant: FUJITSU LIMITED
Inventor： Yasuo Hidaka
CPC classification number: H05K1/0245 , H01P3/08 , H05K1/024 , H05K1/0248 , H05K1/0313 , H05K1/0366 , H05K1/038 , H05K3/0091 , H05K3/10 , H05K3/4644 , H05K2201/0183 , H05K2201/07 , H05K2203/0195
Abstract: A circuit may be configured to reduce electrical signal degradation. The circuit may include a first trace and a second trace that may be broadside coupled between a first ground plane and a second ground plane. The first and second traces may be configured to carry first and second signals, respectively, of a differential signal. The circuit may also include a first dielectric material disposed between the first trace and the second trace. Further, the circuit may include a second dielectric material disposed between the first trace and the first ground plane and disposed between the second trace and the second ground plane. A difference between a first dielectric constant of the first dielectric material and a second dielectric constant of the second dielectric material may suppress a mode conversion of the differential signal from a differential mode to a common mode.
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18.发明申请DEFORMATION SENSING FLEXIBLE SUBSTRATE USING PATTERN FORMED OF CONDUCTIVE MATERIAL 有权使用形成导电材料的图案形成感应柔性基板公开(公告)号：US20170048965A1
公开(公告)日：2017-02-16
申请号：US14895944
申请日：2015-03-11
Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
Inventor： Maenghyo CHO , Kyu Jin CHO , Junghyun RYU , Je Sung KOH , Jong Gu LEE
CPC classification number: H05K1/028 , G01B7/18 , G01B7/20 , G01N27/00 , G01N27/02 , G01R27/00 , G01R27/02 , G01R27/08 , H05K1/02 , H05K3/12 , H05K2201/07
Abstract: Disclosed herein is a deformation sensing flexible substrate using a pattern formed of a conductive material. The deformation sensing flexible substrate, using the pattern formed of the conductive material, includes a flexible substrate; and conductive patterns in which conductors including a conductive material are arranged and formed to be contactable and non-contact to each other based on deformation of the flexible substrate.
Abstract translation: 本文公开了使用由导电材料形成的图案的变形感测柔性基板。 使用由导电材料形成的图案的变形感测柔性基板包括柔性基板; 并且其中导体包括导电材料的导电图案基于柔性基板的变形被布置和形成为彼此接触和不接触。
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公开(公告)号：US20160150633A1
公开(公告)日：2016-05-26
申请号：US14947091
申请日：2015-11-20
Applicant: Amphenol Corporation
Inventor： Marc B. Cartier, JR.
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector; dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and ground vias configured to accept contact tails of ground conductors of the connector.
Abstract translation: 印刷电路板包括多个层，包括附着层和布线层; 以及形成在所述多个层中的通孔图案，所述通孔图案中的每一个包括：形成差分信号对的双直径第一和第二信号通孔，所述第一和第二信号通孔被配置为接纳连接器的信号导体的接触尾部; 与第一和第二信号通孔中的每一个相邻的双直径地面阴影通孔，其中双直径阴影接地通孔相对于双直径第一和第二信号通孔具有反向直径构型; 以及配置为接受连接器的接地导体的接触尾部的接地通孔。
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20.发明授权公开(公告)号：US09198289B2
公开(公告)日：2015-11-24
申请号：US14061500
申请日：2013-10-23
Applicant: Tyco Electronics Corporation
Inventor： Steven Richard Bopp , Neil Ktul Nay
IPC: H01R13/6469 , H05K1/11 , H01R13/6461 , H05K1/02 , H01R13/6466 , H01R24/64 , H01R107/00
CPC classification number: H01R13/6466 , H01R13/6461 , H01R13/6469 , H01R24/64 , H01R2107/00 , H05K1/0228 , H05K1/0239 , H05K1/11 , H05K2201/07 , H05K2201/10189
Abstract: An electrical connector that includes a circuit board having a board substrate that has opposite board surfaces and a thickness measured along an orientation axis that extends between the opposite board surfaces. The circuit board has associated pairs of input and output terminals and signal traces that electrically connect the associated pairs of input and output terminals. The input and output terminals being configured to communicatively coupled to mating and cable conductors, respectively. Each associated pair of input and output terminals is electrically connected through a corresponding signal trace that has a conductive path extending along the board substrate between the corresponding input and output terminals. At least two signal traces form a broadside-coupling region in which the conductive paths of the at least two signal traces are stacked along the orientation axis and spaced apart through the thickness and extend parallel to each other for a crosstalk-reducing distance.
Abstract translation: 一种电连接器，包括具有板基板的电路板，该基板具有相对的板表面，并且沿着在相对的板表面之间延伸的取向轴线测量的厚度。 电路板具有相关联的输入和输出端子对以及电连接相关联的输入和输出端子对的信号迹线。 输入和输出端子分别被配置为可通信地耦合到配合电缆导体和电缆导体。 每个相关联的输入和输出端子对通过相应的信号迹线电连接，该对应的信号迹线具有沿对应的输入和输出端子之间的板基板延伸的导电路径。 至少两个信号迹线形成宽侧耦合区域，其中至少两个信号迹线的导电路径沿着取向轴线堆叠并且间隔开厚度并且彼此平行延伸以减少串扰减小距离。
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