公开(公告)号：US07697262B2

公开(公告)日：2010-04-13

申请号：US12193498

申请日：2008-08-18

Applicant: Andrew P. Ritter ,  John L. Galvagni

Inventor： Andrew P. Ritter ,  John L. Galvagni

IPC: H01G4/228

CPC classification number: H01G4/232 ,  H01C1/148 ,  H01C7/18 ,  H01G2/065 ,  H01G4/012 ,  H01G4/30 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/0792 ,  Y10T29/435

Abstract: Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device. Terminations may also be formed on the top surface (opposite a designated mounting surface) and may be a mirror image, reverse-mirror image, or different shape relative to the bottom surface.

Abstract translation: 低电感电容器包括布置在电介质层之间并定向为使得电极基本上垂直于安装表面的电极。 垂直电极沿着器件外围露出，以确定在哪里形成终端焊盘，限定了焊盘之间的狭窄和可控的间距，用于减小电流环路面积，从而降低了元件电感。 可以通过叉指式终端来提供电流回路面积和部件等效串联电感（ESL）的进一步减小。 端接可以通过各种无电镀技术形成，并且可以直接焊接到电路板焊盘。 端子也可以位于电容器的“端部”上，以实现电气测试或控制焊接圆角尺寸和形状。 可以在设备的给定底部（安装）表面上形成两端子器件以及具有多个端子的器件。 端子也可以形成在顶表面（与指定的安装表面相对）上，并且可以是镜像，反向镜像或相对于底表面的不同形状。

公开(公告)号：US07687391B2

公开(公告)日：2010-03-30

申请号：US11535700

申请日：2006-09-27

Applicant: Paul M. Harvey ,  Kazushige Kawasaki ,  Gen Yamada

Inventor： Paul M. Harvey ,  Kazushige Kawasaki ,  Gen Yamada

IPC: H01L21/4763

CPC classification number: H05K1/116 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09809 ,  H01L2924/00

Abstract: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.

Abstract translation: 提供了用于多层互连基板中的高速信号的电学优化和结构保护的微通孔结构。 通孔结构消除了与参考平面的接触的重叠，从而减小了通孔电容，从而减小了通孔结构中的通路阻抗失配。 结果，通孔结构被电学优化。 通孔结构还包括一个或多个浮动支撑构件，该浮动支撑构件在通孔和参考平面之间的通孔间隙区域内靠近通孔放置。 浮动支撑构件在它们不与通孔或参考平面电接触的意义上是“浮动的”。 因此，它们不是用于信号传播的目的，而是仅用于结构支持。 浮动支撑构件可以通过一个或多个微孔结构相互连接。

公开(公告)号：US20100073350A1

公开(公告)日：2010-03-25

申请号：US12504220

申请日：2009-07-16

Applicant: Yongman Lee

Inventor： Yongman Lee

IPC: G09G5/00 ,  G06F3/038

CPC classification number: G09G3/3655 ,  G02F2001/133328 ,  G02F2001/133331 ,  G02F2201/46 ,  G09G2300/0426 ,  H05K1/0237 ,  H05K1/162 ,  H05K1/189 ,  H05K2201/0792 ,  H05K2201/10136

Abstract: Visual artifacts in a display are reduced by moving, to the extent possible, display driver components to the display surface itself, thereby shortening conductor distances and reducing the parasitic effects caused by parasitic resistance of the conductors between the display power supply and the display, and between the stabilizing capacitors and the display. To avoid interference with the device housing, low-profile driver components, including either or both of stabilizing capacitors and power supply terminals, can be provided and bonded to the surface of the display side of the outer layer of the display. Alternatively, the stabilizing capacitors can be formed on the display side in the same way that, e.g., in an LCD display, the transparent electrodes for controlling the liquid crystals are formed.

Abstract translation: 通过在可能的范围内移动显示器表面本身的显示驱动器组件来减少显示器中的视觉赝像，从而缩短导体距离并减少由于显示电源和显示器之间的导体的寄生电阻引起的寄生效应，以及 在稳定电容器和显示器之间。 为了避免与设备壳体的干涉，可以提供包括稳定电容器和电源端子中的一个或两者的低调驱动器部件并将其结合到显示器的外层的显示侧的表面。 或者，稳定化电容器可以以与例如LCD显示器相同的方式在显示器侧上形成，形成用于控制液晶的透明电极。

公开(公告)号：US07649265B2

公开(公告)日：2010-01-19

申请号：US11541124

申请日：2006-09-29

Applicant: Chunfei Ye ,  Boping Wu

Inventor： Chunfei Ye ,  Boping Wu

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2223/6616 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/112 ,  H05K1/165 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: In some embodiments, a micro-via structure design for high performance integrated circuits is presented. In this regard, an integrated circuit chip package is introduced having a dielectric layer, a plated throughhole in the dielectric layer, and a micro-via coupled with the plated throughhole, wherein the micro-via forms a path around an axis. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，提出了用于高性能集成电路的微通孔结构设计。 在这方面，引入集成电路芯片封装，其具有电介质层，电介质层中的电镀通孔和与电镀通孔耦合的微通孔，其中微通孔围绕轴线形成路径。 还公开并要求保护其他实施例。

公开(公告)号：US20090047755A1

公开(公告)日：2009-02-19

申请号：US12250420

申请日：2008-10-13

Applicant: Yoshiyuki Yamaji ,  Hirokazu Noma ,  Hiroyuki Mori

Inventor： Yoshiyuki Yamaji ,  Hirokazu Noma ,  Hiroyuki Mori

IPC: H01L21/00 ,  H01R9/00

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/30105 ,  H05K1/0216 ,  H05K3/4015 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/0792 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09909 ,  H05K2201/09981 ,  H05K2203/0113 ,  H05K2203/0235 ,  H05K2203/0338 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12, and an IC chip, mounted on the obverse face of the multilayer wiring board 12, and multiple bump terminals 16, mounted on the reverse face. Each bump terminal 16 includes an insulating core 42 having a flat face 40 and a conductive coating deposited on all external surfaces except that of the flat face 40. The end faces of the conductive coatings 44 appear like rings around the insulating cores 42, and are soldered to annular connection pads 52 formed on the reverse face of the multilayer printed wiring board 12. Vias 36 are arranged immediately above the bump terminals 16, and clearance holes 34, the diameter of which is smaller than the diameter of the bump terminals 16, are formed in internal wiring patterns 28 and 30 to permit the passage of the vias 36.

Abstract translation: 提供了具有优异的高频特性并且可以获得用于内部布线图案的大面积的半导体封装。 根据本发明，半导体封装包括：安装在多层布线板12的正面上的多层印刷布线板12和IC芯片以及安装在反面上的多个凸点端子16。 每个凸块端子16包括具有平坦面40的绝缘芯42和沉积在除了平面40之外的所有外表面上的导电涂层。导电涂层44的端面看起来像围绕绝缘芯42的环，并且是 焊接到形成在多层印刷电路板12的背面上的环形连接焊盘52.通孔36布置在凸块端子16的正上方，并且直径小于凸块端子16的直径的间隙孔34， 形成在内部布线图案28和30中以允许通孔36通过。

公开(公告)号：US20080277153A1

公开(公告)日：2008-11-13

申请号：US11931698

申请日：2007-10-31

Applicant: Abeye Teshome ,  Lan Zhang

Inventor： Abeye Teshome ,  Lan Zhang

IPC: H01R12/06

CPC classification number: H05K1/0216 ,  H05K1/0263 ,  H05K1/112 ,  H05K1/162 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/10734 ,  Y10T29/49128 ,  Y10T29/49169

Abstract: Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.

Abstract translation: 通过电路板提供给信息处理系统电子元件的功率具有通过配置与电子元件的连接以补偿寄生电容的组件封装电感寄生效应。 例如，将处理器连接到电路板的电源和接地平面的电源和接地通孔被对准以产生期望的寄生电容，其减少与信号补偿，功率输送和高速解耦有关的寄生电感的影响。 期望的分布电容通过改变与功率通孔的等效线电荷相关联的半径，与电源和接地通孔之间的线路电荷相关联的距离以及通孔筒长度来建模。

公开(公告)号：US20080272862A1

公开(公告)日：2008-11-06

申请号：US12171602

申请日：2008-07-11

Applicant: Paul M. Harvey ,  Kazushige Kawasaki ,  Gen Yamada

Inventor： Paul M. Harvey ,  Kazushige Kawasaki ,  Gen Yamada

IPC: H01P1/00

CPC classification number: H05K1/116 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09809 ,  H01L2924/00

Abstract: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.

公开(公告)号：US20080268666A1

公开(公告)日：2008-10-30

申请号：US12139165

申请日：2008-06-13

Applicant: David A. Johnson ,  Eric V. Kline

Inventor： David A. Johnson ,  Eric V. Kline

IPC: H01R12/00

CPC classification number: H01R13/2464 ,  H01L23/64 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/57 ,  H01R13/2407 ,  H01R13/6464 ,  H01R13/6471 ,  H01R13/6473 ,  H01R13/6608 ,  H01R13/719 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/025 ,  H05K7/1092 ,  H05K2201/0792 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: An apparatus for providing a controlled impedance directly to predetermined contact elements within a socket, thereby reducing the “distorting” nature of the electrical interconnection system. In an illustrative embodiment of the present invention, predetermined contacts of a socket may have a resistance, inductance, capacitance, or a combination thereof incorporated therein. In another illustrative embodiment, at least one active element(s) may also be incorporated into predefined contacts. In this manner, predefined contacts may “process” the corresponding signal in a predetermined manner, defined by the circuitry incorporated on the contact itself. Illustrative functions that may be performed include, but are not limited to, amplifying, analog-to-digital converting, digital-to-analog converting, predefined logic functions, or any other function that may be performed via a combination of active and/or passive elements including a microprocessor function.

Abstract translation: 一种用于将受控阻抗直接提供给插座内的预定接触元件的设备，由此降低了电互连系统的“变形”性质。 在本发明的说明性实施例中，插座的预定触点可以具有并入其中的电阻，电感，电容或其组合。 在另一说明性实施例中，至少一个有源元件也可以并入预定义的触点中。 以这种方式，预定义的触点可以以预定的方式“处理”对应的信号，由接合体本身所包含的电路定义。 可以执行的说明性功能包括但不限于放大模数转换，数模转换，预定义逻辑功能或可以通过有源和/或数字转换的组合来执行的任何其他功能， 无源元件包括微处理器功能。

公开(公告)号：US07402757B1

公开(公告)日：2008-07-22

申请号：US11133499

申请日：2005-05-19

Applicant: Leesa M. Noujeim

Inventor： Leesa M. Noujeim

IPC: H01R12/04

CPC classification number: H05K1/0216 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: A printed circuit board (PCB) is provided. The PCB includes a signal layer, a first reference plane defined adjacent to a first side of the signal layer, and a via passing through the signal layer and the first reference plane. The first side of the signal layer is either above the signal layer or below the signal layer. The via is configured to accept an electrical signal to be routed on the signal layer. The inner area of the first reference plane up to the via is capable of being eliminated.

Abstract translation: 提供印刷电路板（PCB）。 PCB包括信号层，与信号层的第一侧邻近定义的第一参考平面以及通过信号层和第一参考平面的通路。 信号层的第一面是信号层之上或信号层之下。 通孔被配置为接受要在信号层上路由的电信号。 能够消除直到通孔的第一参考平面的内部区域。

公开(公告)号：US07378743B2

公开(公告)日：2008-05-27

申请号：US11453163

申请日：2006-06-13

Applicant: Sheng-Yuan Lee

Inventor： Sheng-Yuan Lee

IPC: H01L23/48

CPC classification number: H01L23/3107 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3442 ,  H05K2201/0792 ,  H05K2201/10689 ,  H05K2201/10727 ,  H05K2201/10931 ,  H05K2201/10969 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A circuit board suitable for being electrically connected to a chip package is provided. The chip package has a chip pad and a plurality of inner leads. The circuit board includes at least one patterned conductive layer and at least one insulating layer. The patterned conductive layer has at least one first pad and at least one second pad. The first pad has an extension part and is suitable for being electrically connected to the chip pad. The second pad is suitable for being electrically connected to one end of at least one of the inner leads, while the other end of the inner lead suitable for being electrically connected to the second pad has a projection at least partially overlapping the extension part on the patterned conductive layer. Moreover, the patterned conductive layer is disposed outside the insulating layer.

Abstract translation: 提供了适于电连接到芯片封装的电路板。 芯片封装具有芯片焊盘和多个内部引线。 电路板包括至少一个图案化导电层和至少一个绝缘层。 图案化导电层具有至少一个第一焊盘和至少一个第二焊盘。 第一焊盘具有延伸部分，并且适于电连接到芯片焊盘。 第二垫适于电连接到至少一个内引线的一端，而内引线的另一端适于与第二焊盘电连接，其突出部分至少部分地与第二焊盘上的延伸部分重叠 图案化导电层。 此外，图案化导电层设置在绝缘层的外部。