公开(公告)号：US20160049240A1

公开(公告)日：2016-02-18

申请号：US14926444

申请日：2015-10-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru KATO

IPC: H01G4/002 ,  H05K1/18 ,  H01G4/26

CPC classification number: H01G4/002 ,  H01G4/14 ,  H01G4/228 ,  H01G4/26 ,  H01G4/33 ,  H05K1/162 ,  H05K1/189 ,  H05K2201/055 ,  H05K2201/09309 ,  H05K2201/10189

Abstract: A flexible cable includes an elongated flexible substrate including first and second surfaces on opposite sides thereof, a first capacitor electrode provided on the first surface side of the flexible substrate, the first capacitor electrode extending from a first end of the flexible substrate toward a second end of the flexible substrate, a second capacitor electrode provided on the second surface side of the flexible substrate, the second capacitor electrode extending from the second end of the flexible substrate toward the first end of the flexible substrate, a first connection portion provided at an end of the first capacitor electrode located at the first end of the flexible substrate, and a second connection portion provided at an end of the second capacitor electrode located at the second end of the flexible substrate.

Abstract translation: 柔性电缆包括细长的柔性基板，其包括在其相对侧上的第一和第二表面，设置在柔性基板的第一表面侧上的第一电容器电极，第一电容器电极从柔性基板的第一端朝向第二端 柔性基板的第二表面侧的第二电容电极，从柔性基板的第二端朝向柔性基板的第一端延伸的第二电容电极，设置在柔性基板的第一端的第一连接部 位于柔性基板的第一端的第一电容器电极和设置在位于柔性基板的第二端的第二电容器电极的端部的第二连接部。

公开(公告)号：US09226397B2

公开(公告)日：2015-12-29

申请号：US13936420

申请日：2013-07-08

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/16 ,  H05K1/09 ,  H01L23/498 ,  H05K1/02 ,  H05K1/05 ,  H05K1/18 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为具有15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：US09101070B2

公开(公告)日：2015-08-04

申请号：US13185295

申请日：2011-07-18

Applicant: Hironori Tanaka ,  Keisuke Shimizu

Inventor： Hironori Tanaka ,  Keisuke Shimizu

IPC: H05K1/16 ,  H05K1/09 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K1/09 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/4913

Abstract: A multilayer printed wiring board includes a core substrate, a resin insulation layer laminated on the core substrate and a capacitor section coupled to the resin insulating layer. The capacitor section includes a first electrode including a first metal and configured to be charged by a negative charge, and a second electrode including a second metal and opposing the first electrode, the second electrode configured to be charged by a positive charge. A dielectric layer is interposed between the first electrode and second electrode, and an ionization tendency of the first metal is larger than and ionization tendency of the second metal.

Abstract translation: 多层印刷线路板包括芯基板，层叠在芯基板上的树脂绝缘层和耦合到树脂绝缘层的电容器部分。 电容器部分包括第一电极，其包括第一金属并被构造为通过负电荷充电;以及第二电极，包括第二金属并与第一电极相对，第二电极被配置为通过正电荷充电。 电介质层插入在第一电极和第二电极之间，第一金属的电离倾向大于第二金属的离子化倾向。

公开(公告)号：US09101054B2

公开(公告)日：2015-08-04

申请号：US13835505

申请日：2013-03-15

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/11 ,  H05K1/02 ,  H01L21/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H05K3/46 ,  H05K1/14 ,  H05K1/18

CPC classification number: H05K1/0237 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/0224 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09736 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer printed wiring board includes a core substrate having a through-hole formed through the substrate, an interlayer insulation layer formed on the substrate and having a via conductor formed through the insulation layer, and a conductor layer formed on the insulation layer and connected to the via in the insulation layer. The substrate has multiplayer insulation structure, outer power layer formed on surface of the structure, outer ground layer formed on opposite surface of the structure, inner power layer formed inside the structure and inner ground layer formed inside the structure, each of the inner layers has tapered end having angle satisfying 2.8

Abstract translation: 多层印刷电路板包括具有通过基板形成的通孔的芯基板，形成在基板上并具有通过绝缘层形成的通孔导体的层间绝缘层，以及形成在绝缘层上的导体层， 绝缘层中的通孔。 所述基板具有多层绝缘结构，在所述结构的表面上形成的外层电力层，在所述结构的相对面上形成的外部地层，在所述结构内形成的内部电力层和在所述结构内形成的内部地层， 锥形端部具有满足2.8

公开(公告)号：US20150041859A1

公开(公告)日：2015-02-12

申请号：US13962622

申请日：2013-08-08

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer

IPC: H01L23/522 ,  H01L29/778

CPC classification number: H01L23/5226 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/48091 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/0761 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09972 ,  H01L2924/00014

Abstract: A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.

Abstract translation: 再分配板包括：第一导电层，包括用于低电压信号的再分配结构;第二导电层，包括用于高电压信号的再分配结构;以及非导电层。 第二导电层通过非导电层与第一导电层间隔开。 再分配板还包括从再分布板的安装表面延伸到第二导电层的导电连接器。 导电连接器被第一导电层的低电压迹线围绕。

公开(公告)号：US08939604B2

公开(公告)日：2015-01-27

申请号：US13423142

申请日：2012-03-16

Applicant: Gerald Edward Briggs

Inventor： Gerald Edward Briggs

IPC: F21S9/00 ,  H01L33/48 ,  H05B37/02 ,  H05B33/08

CPC classification number: H05B33/0827 ,  F21K9/60 ,  F21K99/00 ,  F21S4/20 ,  F21V23/005 ,  F21V23/04 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/62 ,  H01L2924/0002 ,  H05B33/0803 ,  H05B33/0845 ,  H05B33/0857 ,  H05K1/05 ,  H05K2201/09309 ,  H05K2201/09972 ,  H05K2201/10106 ,  H01L2924/00

Abstract: A LED based lighting apparatus is disclosed. The light engine used in the lighting apparatus may use a multi-layer metal core printed circuit board and have a plurality of LED groups that are independently controllable by a control unit. The power supply input and return paths connected to each LED group may be implemented on different layers to allow a compact footprint that may be used with traditional fluorescent encasements with relatively little modification.

Abstract translation: 公开了一种基于LED的照明装置。 在照明装置中使用的光引擎可以使用多层金属芯印刷电路板，并且具有可由控制单元独立控制的多个LED组。 连接到每个LED组的电源输入和返回路径可以在不同的层上实现，以允许紧凑的占地面积可以与具有相对较少修改的传统荧光灯罩一起使用。

公开(公告)号：US08890761B2

公开(公告)日：2014-11-18

申请号：US13057032

申请日：2009-07-31

Applicant: Hiroshi Toyao ,  Noriaki Ando

Inventor： Hiroshi Toyao ,  Noriaki Ando

IPC: H01Q19/00 ,  H01Q21/08 ,  H01Q9/42 ,  H01P5/02 ,  H01P1/20 ,  H05K1/02 ,  H01Q9/04 ,  H05K1/16

CPC classification number: H01Q9/42 ,  H01P1/2005 ,  H01P5/028 ,  H01Q9/0407 ,  H01Q21/08 ,  H05K1/0236 ,  H05K1/165 ,  H05K2201/09309

Abstract: A structure includes a first conductor plane; a plurality of second conductor planes, at least a portion thereof being provided facing the first conductor plane; a transmission line that is provided with at least a portion thereof facing one conductor plane of the first conductor plane and the second conductor plane, and that is disposed on an opposite side of the other conductor plane with respect to the one conductor plane; and a first conductor connecting portion that electrically connects the transmission line with the other conductor plane, and a unit structure that includes at least the second conductor plane, the transmission line, and the first conductor connecting portion is repeatedly disposed.

Abstract translation: 一种结构包括第一导体平面; 多个第二导体平面，其至少一部分面向第一导体平面设置; 传输线设置有至少一部分面对第一导体平面和第二导体平面的一个导体平面，并且相对于一个导体平面设置在另一个导体平面的相对侧上; 以及将所述传输线与所述另一个导体平面电连接的第一导体连接部，以及至少包括所述第二导体平面，所述传输线和所述第一导体连接部的单元结构。

公开(公告)号：US20140300429A1

公开(公告)日：2014-10-09

申请号：US14312971

申请日：2014-06-24

Applicant: Hiroshi Toyao

Inventor： Hiroshi Toyao

IPC: H01P3/00

CPC classification number: H01P3/026 ,  H01P1/2005 ,  H01P1/2013 ,  H01P3/006 ,  H01P3/081 ,  H01P5/028 ,  H01P7/082 ,  H01Q9/04 ,  H05K1/0236 ,  H05K1/165 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09309

Abstract: A waveguide structure or a printed-circuit board is formed using a plurality of unit structures which are repetitively aligned in a one-dimensional manner or in a two-dimensional manner. The unit structure includes first and second conductive planes which are disposed in parallel with each other, a transmission line having an open end which is formed in a layer different from the first and second conductive planes and positioned to face the second conductive plane, and a conductive via electrically connecting the transmission line to the first conductive plane.

公开(公告)号：US08853560B2

公开(公告)日：2014-10-07

申请号：US13411005

申请日：2012-03-02

Applicant: Dae-Hyun Park ,  Han Kim ,  Mi-Ja Han ,  Ja-Bu Koo

Inventor： Dae-Hyun Park ,  Han Kim ,  Mi-Ja Han ,  Ja-Bu Koo

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0236 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09781 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T428/12465

Abstract: An electromagnetic bandgap structure and a printed circuit board that solve a mixed signal problem are disclosed. In accordance with embodiments of the present invention, the electromagnetic bandgap structure includes a first metal layer; a first dielectric layer, stacked in the first metal layer; a second metal layer, stacked in the first dielectric layer, and having a holed formed at a position of the second dielectric layer; a second dielectric layer, stacked in the second metal layer; a metal plate, stacked in the second dielectric layer; a first via, penetrating the hole formed in the second metal layer and connecting the first metal layer and the metal plate; a third dielectric layer, stacked in the metal plate and the second dielectric layer; a third metal layer, stacked in the third dielectric layer; and a second via, connecting the second metal layer to the third metal layer.

Abstract translation: 公开了一种解决混合信号问题的电磁带隙结构和印刷电路板。 根据本发明的实施例，电磁带隙结构包括第一金属层; 第一介电层，堆叠在第一金属层中; 第二金属层，堆叠在第一介电层中，并且具有形成在第二介电层的位置的孔; 第二介电层，堆叠在第二金属层中; 金属板，堆叠在第二介电层中; 穿过形成在第二金属层中的孔并连接第一金属层和金属板的第一通孔; 第三电介质层，堆叠在所述金属板和所述第二介电层中; 第三金属层，堆叠在第三介电层中; 以及将第二金属层连接到第三金属层的第二通孔。

公开(公告)号：US08847574B2

公开(公告)日：2014-09-30

申请号：US13498086

申请日：2010-09-23

Applicant: Iain Barnett ,  Jonathan Ephraim David Hurwitz ,  William Michael James Holland

Inventor： Iain Barnett ,  Jonathan Ephraim David Hurwitz ,  William Michael James Holland

IPC: H04B3/00 ,  H04B3/56

CPC classification number: H04B3/56 ,  H05K1/0256 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09972

Abstract: Disclosed is an electrical isolator circuit comprising an input stage comprising first and second inputs, the input stage being configured to receive an input voltage signal; an output stage comprising first and second outputs electrically connected across a load capacitor; and a DC isolator comprising a first capacitor between said first input and said first output and second capacitor between said second input and said second output. The first and second plates of each of the first, second and load capacitors are defined by conductive layers of a printed circuit board and the dielectric of each of the first, second and load capacitors are defined by a non-conducting part of the printed circuit board.

Abstract translation: 公开了一种电气隔离器电路，包括具有第一和第二输入的输入级，输入级被配置为接收输入电压信号; 输出级包括跨过负载电容器电连接的第一和第二输出; 以及直流隔离器，其包括在所述第一输入和所述第一输出之间的第一电容器和在所述第二输入和所述第二输出之间的第二电容器。 第一，第二和负载电容器中的每一个的第一和第二板由印刷电路板的导电层限定，并且第一，第二和负载电容器中的每一个的电介质由印刷电路的不导电部分限定 板。