公开(公告)号：US20130235543A1

公开(公告)日：2013-09-12

申请号：US13873504

申请日：2013-04-30

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Junichi Nakamura ,  Yuji Kobayashi

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/116 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2203/0338 ,  H05K2203/0361 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.

Abstract translation: 制造布线板的方法包括在支撑板上形成限定开口部分的焊料或电镀抗蚀剂层的抗蚀剂层，使得支撑板的一部分露出。 电极直接形成在开口部内的支撑板上，当使用时，电镀抗蚀剂层被去除。 在电极以及支撑板或阻焊层上形成绝缘层，并且还形成连接到绝缘层处的电极的布线部分。 然后在布线部分上形成具有开口部分的阻焊层，并且去除支撑板以暴露电极的表面或电极和绝缘层的表面。 然后可以在绝缘层的暴露表面上形成具有开口部分的另一阻焊层。

公开(公告)号：US20130109244A1

公开(公告)日：2013-05-02

申请号：US13609584

申请日：2012-09-11

Applicant: CHIH-JUNG CHEN

Inventor： CHIH-JUNG CHEN

IPC: H01R13/11

CPC classification number: H01R24/62 ,  H01R12/62 ,  H01R2107/00 ,  H05K1/117 ,  H05K3/34 ,  H05K2201/0715 ,  H05K2201/0949 ,  H05K2201/10303 ,  H05K2201/10356

Abstract: An electrical connector assembly is provided with an insulating housing, a PCB, and an FFC. The insulating housing includes a plurality of terminals. The FFC and the terminals are electrically connected together by the PCB. The PCB is vertically secured to a rear end of the insulating housing. A plurality of contacts of the PCB are provided on a rear surface of the PCB.

Abstract translation: 电连接器组件设置有绝缘壳体，PCB和FFC。 绝缘壳体包括多个端子。 FFC和端子通过PCB电连接在一起。 PCB垂直固定在绝缘外壳的后端。 PCB的多个触点设置在PCB的后表面上。

公开(公告)号：US20130107468A1

公开(公告)日：2013-05-02

申请号：US13720849

申请日：2012-12-19

Applicant: STEC, INC.

Inventor： Mark MOSHAYEDI

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L23/50 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/09072 ,  H05K2201/0949 ,  H05K2201/10515 ,  H05K2201/10666 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.

Abstract translation: 多芯片堆叠模块为给定的表面芯片占用空间提供了增加的电路密度。 支撑结构与标准表面贴装型芯片交替形成堆叠，其中支撑结构将芯片电互连。 一个方面是用于在垂直堆叠中互连多个大致平面的芯片的结构和方法，使得在堆叠中共同连接的芯片的信号和单独访问的信号在堆栈内分离。

公开(公告)号：US20130083505A1

公开(公告)日：2013-04-04

申请号：US13609690

申请日：2012-09-11

Applicant: Noriyuki Kobayashi

Inventor： Noriyuki Kobayashi

IPC: H05K1/14 ,  H01R24/00 ,  H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/11 ,  H05K1/117 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/09409 ,  H05K2201/0949

Abstract: Disclosed herein is a wiring board including: a differential-line pair including two lines for transmitting differential signals; and two connection pads each electrically connected to one of the two lines pertaining to one of the differential-line pairs, wherein a plurality of the differential-line pairs are laid out side by side; a plurality of the connection pads are provided to form a plurality of columns; and on each of the columns of the connection pads, any two the connection pads electrically connected to the lines pertaining to the same differential-line pair are provided at locations adjacent to each other on the same one of the columns.

Abstract translation: 这里公开了一种布线板，包括：差分线对，包括用于传输差分信号的两条线; 以及两个连接焊盘，每个连接焊盘电连接到属于所述差分线对之一的两条线之一，其中多个所述差分线对并排布置; 提供多个连接焊盘以形成多个列; 并且在连接焊盘的每个列上，电连接到与相同的差分线对相关的线的任何两个连接焊盘设置在相同的一个列上彼此相邻的位置处。

公开(公告)号：US20120318852A1

公开(公告)日：2012-12-20

申请号：US13524245

申请日：2012-06-15

Applicant: Wen-Bing ZHOU ,  Youg-Jun LIAO ,  Qiang WANG ,  Hung-Che CHEN

Inventor： Wen-Bing ZHOU ,  Youg-Jun LIAO ,  Qiang WANG ,  Hung-Che CHEN

IPC: B23K31/02 ,  H05K9/00

CPC classification number: H05K9/0039 ,  H05K1/0215 ,  H05K3/3468 ,  H05K2201/09418 ,  H05K2201/0949 ,  H05K2201/10409 ,  H05K2203/044

Abstract: A method of preventing EMI for a fastening hole in a circuit board includes the steps of providing a circuit board which includes a plurality of fastening holes extending through opposite first and second surfaces thereof and a plurality of solder pads disposed on the second surface, each fastening hole being surrounded by the solder pads; disposing an electronic component on the first surface; positioning the circuit board on a fixture such that the solder pads are not covered by the fixture; and wave soldering the circuit board so that the electronic component is fixed to the circuit board and the solder pads are attached with solder materials.

Abstract translation: 防止EMI对电路板中的紧固孔的方法包括以下步骤：提供电路板，其包括延伸穿过其相对的第一和第二表面的多个紧固孔以及设置在第二表面上的多个焊盘，每个紧固 孔被焊垫包围; 在第一表面上设置电子部件; 将电路板定位在固定装置上，使得焊盘不被夹具覆盖; 并且将电路板波峰焊接，使得电子部件固定到电路板，并且焊盘用焊料材料附着。

公开(公告)号：US08288661B2

公开(公告)日：2012-10-16

申请号：US12617191

申请日：2009-11-12

Applicant: Osamu Daikuhara ,  Toshihiro Kusagaya ,  Toru Yamakami ,  Takahiro Kondou

Inventor： Osamu Daikuhara ,  Toshihiro Kusagaya ,  Toru Yamakami ,  Takahiro Kondou

IPC: H05K1/11

CPC classification number: H05K3/242 ,  H05K1/117 ,  H05K3/0047 ,  H05K3/429 ,  H05K2201/0919 ,  H05K2201/0949 ,  H05K2203/0207 ,  H05K2203/175 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit board of a card edge connector type includes interconnections formed on a surface of a substrate to be electrically coupled to respective connecting terminals formed by electrolytic plating on an edge of the substrate, and connecting terminal-forming wirings being respectively in connection with the interconnections, when the connecting terminals are formed by the electrolytic plating. The interconnections are electrically isolated from the connecting terminal-forming wirings by process openings formed in the substrate.

Abstract translation: 卡边缘连接器类型的印刷电路板包括形成在基板的表面上的互连，该互连电连接到在基板的边缘上由电解电镀形成的各个连接端子，以及连接端子形成布线分别与 当连接端子由电解电镀形成时，互连。 互连通过形成在基板中的工艺开口与连接端子形成布线电隔离。

公开(公告)号：US20120247821A1

公开(公告)日：2012-10-04

申请号：US13436005

申请日：2012-03-30

Applicant: Toshihisa NOMURA ,  Kenji SUZUKI ,  Kazushige AKITA

Inventor： Toshihisa NOMURA ,  Kenji SUZUKI ,  Kazushige AKITA

IPC: H05K1/00 ,  B32B38/10 ,  B05D5/12

CPC classification number: H05K1/0287 ,  G01R1/07342 ,  G01R3/00 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/005 ,  H05K3/4061 ,  H05K3/429 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/0979 ,  Y10T156/11

Abstract: A ceramic substrate for an electronic part inspecting apparatus that can be manufactured in accordance with predetermined specifications, regardless of the number and location of pins required, relatively quickly and inexpensively is provided. In certain embodiments the ceramic substrate is configured to connect to a probe for inspecting an electronic component, and the ceramic substrate comprises a plurality of vias located in a center area of the ceramic substrate that penetrate through the ceramic substrate in its thicknesswise direction, pads located in an outer periphery that surrounds the center area where the vias are located, the pads being configured to connected to the probes, and a conductive layer located only over the front surface of the ceramic substrate and connects the vias to the respective pads. Certain embodiments comprise a greater number of vias than pins. A method of manufacturing the ceramic substrate is also provided.

Abstract translation: 提供了一种用于电子部件检查装置的陶瓷基板，其可以根据预定规格制造，而不管所需的销的数量和位置如何，相对快速且低成本地进行。 在某些实施例中，陶瓷衬底被配置为连接到用于检查电子部件的探针，并且陶瓷衬底包括位于陶瓷衬底的沿其厚度方向穿过陶瓷衬底的中心区域的多个通孔，位于 在围绕通孔所在的中心区域的外周中，衬垫被配置为连接到探针，以及导电层，其仅位于陶瓷衬底的前表面上，并将通孔连接到相应的焊盘。 某些实施例包括比引脚更多的通孔。 还提供了制造陶瓷基板的方法。

公开(公告)号：US20110286189A1

公开(公告)日：2011-11-24

申请号：US13196129

申请日：2011-08-02

Applicant: Junichi Nakamura ,  Yuji Kobayashi

Inventor： Junichi Nakamura ,  Yuji Kobayashi

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/115 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/116 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2203/0338 ,  H05K2203/0361 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.

Abstract translation: 制造布线板的方法包括在支撑板上形成限定开口部分的焊料或电镀抗蚀剂层的抗蚀剂层，使得支撑板的一部分露出。 电极直接形成在开口部内的支撑板上，当使用时，电镀抗蚀剂层被去除。 在电极以及支撑板或阻焊层上形成绝缘层，并且还形成连接到绝缘层处的电极的布线部分。 然后在布线部分上形成具有开口部分的阻焊层，并且去除支撑板以暴露电极的表面或电极和绝缘层的表面。 然后可以在绝缘层的暴露表面上形成具有开口部分的另一阻焊层。

公开(公告)号：US20110124237A1

公开(公告)日：2011-05-26

申请号：US12624929

申请日：2009-11-24

Applicant: Hsuan-Ho CHUNG

Inventor： Hsuan-Ho CHUNG

IPC: H01R24/00

CPC classification number: H01R27/00 ,  H01R12/52 ,  H01R12/58 ,  H01R24/60 ,  H05K1/117 ,  H05K1/141 ,  H05K3/4015 ,  H05K2201/0311 ,  H05K2201/0949 ,  H05K2201/10303 ,  H05K2201/1031 ,  H05K2201/1034 ,  Y02P70/611

Abstract: The present invention relates to a connector, which includes a printed circuit tongue, and one surface of the printed circuit tongue is defined with a plurality of first printed areas and second printed areas which are joined to terminals. Elastic terminal pieces extend from the first printed areas and assembled on the printed circuit tongue, and third printed areas similarly extend from the second printed areas and defined on the printed circuit tongue. Moreover, fourth printed areas are defined on another surface of the printed circuit tongue, and fifth printed areas extend from the fourth printed areas and defined on the printed circuit tongue. Accordingly, the present invention enables achieving a connector that is tough and strong, the manufacturing process of which is simple and fast, and the wire layout is simple.

Abstract translation: 本发明涉及一种连接器，其包括印刷电路舌片，并且印刷电路舌片的一个表面限定有多个第一印刷区域和与端子连接的第二印刷区域。 弹性端子件从第一印刷区域延伸并组装在印刷电路舌上，并且第三印刷区域类似地从第二印刷区域延伸并限定在印刷电路舌上。 此外，第四印刷区域被限定在印刷电路舌片的另一表面上，并且第五印刷区域从第四印刷区域延伸并限定在印刷电路舌片上。 因此，本发明能够实现坚固坚固的连接器，其制造过程简单快捷，线布局简单。

公开(公告)号：US07902651B2

公开(公告)日：2011-03-08

申请号：US10953248

申请日：2004-09-28

Applicant: Mark Moshayedi

Inventor： Mark Moshayedi

IPC: H01L23/02

CPC classification number: H05K1/181 ,  H01L23/50 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/09072 ,  H05K2201/0949 ,  H05K2201/10515 ,  H05K2201/10666 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A multi-chip stack module provides increased circuit density for a given surface chip footprint. The multi-chip stack module comprises support structures alternating with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. Various embodiments disclose a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that common signals are connected in the stack and individually-accessed signals are separated within the stack.

Abstract translation: 多芯片堆叠模块为给定的表面芯片占用空间提供了增加的电路密度。 多芯片堆叠模块包括与标准表面安装型芯片交替的支撑结构，以形成堆叠，其中支撑结构将芯片电连接。 各种实施例公开了用于在垂直堆叠中互连多个大体上平坦的芯片的结构和方法，使得公共信号连接在堆栈中，并且单独访问的信号在堆栈内分离。