公开(公告)号：US20100046185A1

公开(公告)日：2010-02-25

申请号：US12544156

申请日：2009-08-19

Applicant: Hideaki Hirasawa

Inventor： Hideaki Hirasawa

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/00

CPC classification number: H05K1/11 ,  H05K1/0203 ,  H05K1/111 ,  H05K3/3421 ,  H05K3/3452 ,  H05K3/3468 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/10522 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2203/046 ,  Y02P70/611

Abstract: A printed circuit board has a first solder land, a second solder land, and a signal line pattern. The first solder land is configured to be soldered with an electronic part. The second solder land is configured to accumulate solder, the second solder land being disposed on a downstream side of the first solder land as viewed in a direction in which the printed circuit is carried. The signal line pattern includes an exposed part that is not covered with a resist, the exposed part being disposed between the solder land and the solder bridge prevention land.

Abstract translation: 印刷电路板具有第一焊盘焊盘，第二焊盘焊盘和信号线图案。 第一焊盘被配置为与电子部件焊接。 第二焊盘被构造为蓄积焊料，第二焊盘位于沿着印刷电路的携带方向设置在第一焊盘的下游侧。 信号线图案包括未被抗蚀剂覆盖的暴露部分，暴露部分设置在焊接区域和防止桥接防止焊盘之间。

公开(公告)号：US07630208B2

公开(公告)日：2009-12-08

申请号：US12198342

申请日：2008-08-26

Applicant: Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

Inventor： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

IPC: H05K1/16

CPC classification number: H01G4/232 ,  H01G4/012 ,  H01G4/30 ,  H01G4/385 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/09309 ,  H05K2201/09772 ,  H05K2201/0979 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.

Abstract translation: 本发明提供一种多层片状电容器，其包括具有层叠方向配置的第一和第二电容器单元的电容器体; 以及形成在电容器主体外部的多个外部电极。 第一电容器单元包括交替设置在电容器主体的内部的至少一对第一和第二内部电极，第二电容器单元包括交替设置在电容器主体内部的多个第三和第四内部电极， 并且第一至第四内部电极耦合到第一至第四外部电极。 第一电容器单元具有比第二电容器单元更低的等效串联电感（ESL），并且第一电容器单元具有比第二电容器单元更高的等效串联电阻（ESR）。

公开(公告)号：US20090174502A1

公开(公告)日：2009-07-09

申请号：US12404999

申请日：2009-03-16

Applicant: Junichi KURITA ,  Kenji KURANUKI ,  Youichi AOSHIMA ,  Hiroshi HIGASHITANI ,  Tsuyoshi YOSHINO

Inventor： Junichi KURITA ,  Kenji KURANUKI ,  Youichi AOSHIMA ,  Hiroshi HIGASHITANI ,  Tsuyoshi YOSHINO

IPC: H03H7/01 ,  H05K1/16

CPC classification number: H05K1/0231 ,  H01G9/012 ,  H01G9/28 ,  H05K1/165 ,  H05K2201/09772 ,  H05K2201/10015

Abstract: A printed board is mounted with a chip-type solid electrolytic capacitor of a four-terminal structure where a pair of positive electrode terminals are disposed at opposite positions and a pair of negative electrode terminals are disposed at opposite positions on a mounting surface. The printed board has a pair of positive electrode patterns and a pair of negative electrode patterns to which the positive electrode terminals and negative electrode terminals of the chip-type solid electrolytic capacitor are connected, respectively. The printed board further has an inductor section that is insulated from the negative electrode patterns, and electrically connects the positive electrode patterns.

Abstract translation: 印刷电路板安装有四端结构的芯片式固体电解电容器，其中一对正电极端子设置在相对位置，一对负电极端子设置在安装表面上的相对位置。 印刷电路板分别具有一对正电极图案和一对负电极图案，芯片型固体电解电容器的正极端子和负极端子分别连接到负极图案。 印刷电路板还具有与负电极图案绝缘的电感器部分，并且电连接正电极图案。

公开(公告)号：US20070167036A1

公开(公告)日：2007-07-19

申请号：US11652818

申请日：2007-01-12

Applicant: Ock-Jin Kim

Inventor： Ock-Jin Kim

IPC: H01R12/00

CPC classification number: G09G3/3611 ,  G02F1/13452 ,  G09G2320/0223 ,  H01R12/7076 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09772 ,  H05K2201/10674

Abstract: A flexible circuit board includes a base substrate, a driving chip, an input transmission line, an output transmission line and a connecting transmission line. The driving chip is on a surface of the base substrate. The input transmission line is on the surface of the base substrate and electrically connected to an input terminal of the driving chip. The output transmission line is on the surface of the base substrate and electrically connected to an output terminal of the driving chip. The input transmission line is electrically connected to the output transmission line through the connecting transmission line.

Abstract translation: 柔性电路板包括基底基板，驱动芯片，输入传输线，输出传输线和连接传输线。 驱动芯片在基底基板的表面上。 输入传输线在基板的表面上，并与驱动芯片的输入端电连接。 输出传输线位于基底表面上，并与驱动芯片的输出端电连接。 输入传输线通过连接传输线电连接到输出传输线。

公开(公告)号：US07105923B2

公开(公告)日：2006-09-12

申请号：US10103386

申请日：2002-03-21

Applicant: Kevin P. Lyne

Inventor： Kevin P. Lyne

IPC: H01L23/34 ,  H01L23/48

CPC classification number: H01L23/49816 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/113 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.

公开(公告)号：US20060163721A1

公开(公告)日：2006-07-27

申请号：US11040726

申请日：2005-01-21

Applicant: Frederick Kuhlman ,  Brentt Duff ,  Michael Pepples ,  Raymond Anton ,  Daniel Harshbarger

Inventor： Frederick Kuhlman ,  Brentt Duff ,  Michael Pepples ,  Raymond Anton ,  Daniel Harshbarger

IPC: H01L23/10

CPC classification number: H05K3/3452 ,  H05K1/181 ,  H05K3/3442 ,  H05K3/3489 ,  H05K2201/09772 ,  H05K2201/09909 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic assembly includes a substrate and at least one surface mounted electronic component. The substrate includes a first side and a second side opposite the first side. The first side of the substrate includes a plurality of conductive traces formed thereon. The plurality of conductive traces includes a first conductive trace and a second conductive trace. The electronic component is electrically coupled between the first and second conductive traces. A component body of the electronic component is subject to interaction with a flux, which is utilized during electrical coupling of the electronic component to the first and second conductive traces, to form a current leakage path. The substrate is configured to prevent the formation of the current leakage path.

Abstract translation: 电子组件包括基板和至少一个表面安装的电子部件。 基板包括与第一侧相对的第一侧和第二侧。 基板的第一面包括形成在其上的多个导电迹线。 多个导电迹线包括第一导电迹线和第二导电迹线。 电子部件电耦合在第一和第二导电迹线之间。 电子部件的组件主体经受与焊剂的相互作用，焊剂在电子部件与第一和第二导电迹线的电耦合期间被利用，以形成电流泄漏路径。 衬底被配置为防止形成电流泄漏路径。

公开(公告)号：US20040251533A1

公开(公告)日：2004-12-16

申请号：US10813137

申请日：2004-03-29

Inventor： Takeshi Suzuki ,  Kazushige Osumi ,  Junichi Ichihashi ,  Toshiyuki Iimura ,  Shinichi Tsuyuki

IPC: H01L023/48 ,  H01L023/52

CPC classification number: H01L24/49 ,  H01L23/4334 ,  H01L23/49531 ,  H01L24/45 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/056 ,  H05K3/284 ,  H05K3/4046 ,  H05K3/44 ,  H05K2201/09554 ,  H05K2201/09772 ,  H05K2201/10287 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Provided is a hybrid integrated circuit device which can more effectively stabilize a circuit configured to operate at a high speed. A hybrid integrated circuit device of the embodiment includes a metal substrate provided with an insulating layer on a surface thereof, a conductive pattern formed on a surface of the insulating layer, a semiconductor element fixed onto the conductive pattern, a lead as external connecting means fixed to the conductive pattern in the periphery of the metal substrate, and a contact portion for electrically connecting the conductive pattern electrically connected to the semiconductor element to the metal substrate in the vicinity of the semiconductor element.

Abstract translation: 提供了一种混合集成电路器件，其可以更有效地稳定被配置为高速操作的电路。 本实施例的混合集成电路器件包括在其表面上设置有绝缘层的金属基板，形成在绝缘层的表面上的导电图案，固定到导电图案上的半导体元件，固定的外部连接装置的引线 涉及金属基板周边的导电图案，以及用于将与半导体元件电连接的导电图案与半导体元件附近的金属基板电连接的接触部。

公开(公告)号：US06803664B2

公开(公告)日：2004-10-12

申请号：US10123211

申请日：2002-04-17

Applicant: Kei Murayama

Inventor： Kei Murayama

IPC: H01L2940

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K3/4602 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/10318 ,  Y02P70/611 ,  H01L2224/0401

Abstract: A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.

公开(公告)号：US06657275B1

公开(公告)日：2003-12-02

申请号：US09366439

申请日：1999-08-02

Applicant: Chee-Yee Chung ,  David G. Figueroa ,  Yuan-Liang Li

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Yuan-Liang Li

IPC: H01L2900

CPC classification number: H05K1/113 ,  H01L23/5222 ,  H01L23/5286 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K2201/09309 ,  H05K2201/09381 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An integrated circuit package and land side capacitor with reduced power delivery loop inductance. The capacitor pads have vias that lie underneath the land side capacitor, and have interposed digits.

Abstract translation: 集成电路封装和接地侧电容器，具有降低的功率输出环路电感。 电容器垫具有位于陆侧电容器下面的通孔，并且具有插入的数字。

公开(公告)号：US20030053296A1

公开(公告)日：2003-03-20

申请号：US10096509

申请日：2002-03-13

Applicant: Fujitsu Limited

Inventor： Atsuko Tanaka ,  Masuo Ohnishi

IPC: H05K005/00

CPC classification number: H05K1/0272 ,  G06F1/203 ,  H01L2924/0002 ,  H05K1/0209 ,  H05K2201/064 ,  H05K2201/09072 ,  H05K2201/09772 ,  H05K2201/09781 ,  H01L2924/00

Abstract: A fan housing of a fan unit includes a housing wall standing from the surface of a printed circuit board. The printed circuit board serves to establish the fan housing in cooperation with the housing wall. The fan housing further includes a ceiling wall connected to the housing wall. The ceiling wall extends along a datum plane parallel to the surface of the printed circuit board. A high speed airflow can be generated within the fan housing. The airflow promotes the heat radiation from the printed circuit board. An electrically conductive wiring pattern extending over the surface of the printed circuit board may further promote the heat radiation from the printed circuit board.

Abstract translation: 风扇单元的风扇壳体包括从印刷电路板的表面竖立的壳体壁。 印刷电路板用于与壳体壁一起建立风扇壳体。 风扇壳体还包括连接到壳体壁的顶壁。 顶壁沿平行于印刷电路板表面的基准平面延伸。 风扇外壳内可能产生高速气流。 气流促进印刷电路板的热辐射。 在印刷电路板的表面上延伸的导电布线图形可以进一步促进来自印刷电路板的热辐射。