公开(公告)号：US08418357B2

公开(公告)日：2013-04-16

申请号：US12329614

申请日：2008-12-07

Applicant: Yung-Chieh Chen ,  Cheng-Shien Li ,  Shou-Kuo Hsu

Inventor： Yung-Chieh Chen ,  Cheng-Shien Li ,  Shou-Kuo Hsu

IPC: H05K3/30 ,  H01R43/00

CPC classification number: H05K1/0295 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/113 ,  H05K2201/09236 ,  H05K2201/09954 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913

Abstract: A printed circuit board layout method includes the following steps. Providing a printed circuit board with a first layout layer and a second layout layer. Disposing a pair of first conducting portions on the first layout layer to electrically couple to a control chip. Sequentially disposing a pair of second conducting portions, a pair of third conducting portions, and a pair of fourth conducting portions on the second layout layer. Providing a pair of connecting portions to connect the first conducting portions and the third conducting portions. Electrically connecting an electronic device to the second conducting portions, and providing a first and second components are coupled with the third and fourth conducting portions, or electrically coupling the electronic device to the fourth conducting portions, and providing the first and the second components are coupled with the second and third conducting portions.

Abstract translation: 印刷电路板布局方法包括以下步骤。 提供具有第一布局层和第二布局层的印刷电路板。 在第一布局层上布置一对第一导电部分以电耦合到控制芯片。 在第二布局层上顺序地布置一对第二导电部分，一对第三导电部分和一对第四导电部分。 提供一对连接部分以连接第一导电部分和第三导电部分。 将电子设备电连接到第二导电部分，以及提供第一和第二部件与第三和第四导电部分耦合，或将电子器件电耦合到第四导电部分，并且提供第一和第二部件耦合 具有第二和第三导电部分。

公开(公告)号：US08412906B2

公开(公告)日：2013-04-02

申请号：US13365890

申请日：2012-02-03

Applicant: Richard E. Perego ,  Donald C. Stark ,  Frederick A. Ware ,  Ely K. Tsern ,  Craig E. Hampel

Inventor： Richard E. Perego ,  Donald C. Stark ,  Frederick A. Ware ,  Ely K. Tsern ,  Craig E. Hampel

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F13/1678 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1657 ,  G06F13/4022 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1087 ,  G11C8/06 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/105 ,  G11C2207/108 ,  H05K1/117 ,  H05K1/14 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y02D10/14

Abstract: Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

Abstract translation: 描述了组织在存储器子部分中并且包括可配置路由以支持多个数据宽度配置的存储器设备。 相对窄的宽度配置加载较少的读出放大器，导致相对较窄的存储器配置的功率消耗减少。 还描述了将宽度选择信息传送到可配置的存储装置并支持多个宽度配置的点对点数据接口的存储器控​​制器。

公开(公告)号：US20130077270A1

公开(公告)日：2013-03-28

申请号：US13678115

申请日：2012-11-15

Applicant: Hyo-Jae BANG ,  Dogeun KIM ,  Hongkyun KIM ,  Youngbok JEON

Inventor： Hyo-Jae BANG ,  Dogeun KIM ,  Hongkyun KIM ,  Youngbok JEON

IPC: H05K1/11 ,  H05K13/00 ,  H05K3/30 ,  H01R13/00 ,  H05K7/02 ,  H05K3/10

CPC classification number: H05K5/0026 ,  G06F1/18 ,  G06F1/185 ,  G06K7/0047 ,  H01R12/57 ,  H01R12/721 ,  H01R13/00 ,  H01R23/70 ,  H01R27/00 ,  H05K1/0295 ,  H05K1/11 ,  H05K1/117 ,  H05K1/181 ,  H05K3/10 ,  H05K3/303 ,  H05K3/3405 ,  H05K7/02 ,  H05K13/00 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/09954 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10446 ,  Y10S439/946 ,  Y10S439/951 ,  Y10T29/49124 ,  Y10T29/49147

Abstract: Example embodiments are directed to circuit boards, connectors, cases, circuit board assemblies, case assemblies, devices and methods of manufacturing the same, which are common to at least two different form factors.

Abstract translation: 示例性实施例涉及电路板，连接器，外壳，电路板组件，壳体组件，其制造方法及其制造方法，这对于至少两种不同的形状因子是共同的。

公开(公告)号：US08250747B2

公开(公告)日：2012-08-28

申请号：US12826006

申请日：2010-06-29

Applicant: Masaaki Togashi

Inventor： Masaaki Togashi

IPC: H05K3/30

CPC classification number: H05K1/0231 ,  H01G2/065 ,  H01G4/232 ,  H05K1/0295 ,  H05K1/111 ,  H05K2201/09954 ,  Y10T29/417 ,  Y10T29/435 ,  Y10T29/4913

Abstract: A method is provided to mount a capacitor array onto a circuit board formed with first leads for connecting power lines to each other and a second lead for grounding. The method uses one of a first connection method of connecting such that first and second capacitor sections are parallel to each other, third capacitor section is in series with the parallel first and second capacitor sections; a second connection method of connecting such that the first to third capacitor sections are in series in sequence; and a third connection method of connecting such that the first and second capacitor sections are in series with each other without using the third capacitor section.

Abstract translation: 提供了一种将电容器阵列安装到形成有用于将电力线彼此连接的第一引线形成的电路板和用于接地的第二引线的方法。 该方法使用第一和第二电容器部分彼此并联的第一连接方法之一，第三电容器部分与并联的第一和第二电容器部分串联; 连接的第二连接方法，使得第一至第三电容器部分依次串联; 以及连接的第三连接方法，使得第一和第二电容器部分彼此串联而不使用第三电容器部分。

公开(公告)号：US08196297B2

公开(公告)日：2012-06-12

申请号：US12332075

申请日：2008-12-10

Applicant: Keith W. Whites ,  Anthony K Amert ,  Brian B Glover

Inventor： Keith W. Whites ,  Anthony K Amert ,  Brian B Glover

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K3/36 ,  H01P1/20372 ,  H01P11/007 ,  H05K1/0237 ,  H05K1/0295 ,  H05K1/141 ,  H05K1/147 ,  H05K2201/09954 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/5313

Abstract: A method of rapid prototyping of a microwave device, by: providing a plurality of thin sheets of low loss dielectric film, each sheet having a different metallization pattern formed thereon; providing a base onto which each of the plurality of thin sheets of low loss dielectric film can be received, wherein the base comprises a metallization pattern formed thereon such that the placement of each of the plurality of thin sheets thereon forms a different circuit; and sequentially placing each of the plurality of thin sheets of low loss dielectric film onto the base, thereby sequentially forming different circuits across the thin sheet and the base.

Abstract translation: 一种通过以下方式快速成型微波器件的方法：提供多个薄片的低损耗介电膜，每个片材上形成有不同的金属化图案; 提供可以容纳所述多个低损耗介电膜薄片中的每一个的基底，其中，所述基底包括形成在其上的金属化图案，使得所述多个薄片中的每一个在其上的放置形成不同的电路; 并且将多个低损耗电介质薄膜的每一个顺序地放置在基底上，从而顺序地在薄片和基底上形成不同的电路。

公开(公告)号：US08139369B2

公开(公告)日：2012-03-20

申请号：US12102169

申请日：2008-04-14

Applicant: Jeremy F. Weinstein ,  Robert M. Ward

Inventor： Jeremy F. Weinstein ,  Robert M. Ward

IPC: H05K7/10

CPC classification number: H01R12/515 ,  H05K1/0295 ,  H05K1/111 ,  H05K3/32 ,  H05K3/3405 ,  H05K3/3421 ,  H05K2201/09272 ,  H05K2201/09381 ,  H05K2201/09954 ,  H05K2201/10287 ,  H05K2201/10409 ,  Y02P70/611 ,  Y02P70/613

Abstract: A printed wiring board includes solder pads to which component leads may be soldered. L-shaped solder pads of the printed wiring board allow component leads to approach the board from any of the four major sides of the printed wiring board. Each solder pad includes two legs and two respective axes. A component lead may be selectively soldered to one of the two legs of the solder pad. Thus, a component lead may approach a solder pad from one of four orthogonal directions.

Abstract translation: 印刷电路板包括可焊接组件引线的焊盘。 印刷电路板的L形焊盘允许组件导线从印刷电路板的四个主要侧面中的任一侧接近板。 每个焊盘包括两个腿和两个相应的轴。 部件引线可以选择性地焊接到焊盘的两条腿之一。 因此，部件引线可以从四个正交方向之一接近焊盘。

公开(公告)号：US08125488B1

公开(公告)日：2012-02-28

申请号：US11286965

申请日：2005-11-22

Applicant: Thomas E. Dewey

Inventor： Thomas E. Dewey

IPC: G06F15/00

CPC classification number: H05K1/0295 ,  H05K2201/09954 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: An interface device having a video BIOS component. The device includes a substrate for implementing a mother board connection and implementing a GPU (graphics processor unit) connection. A video BIOS component is mounted on the substrate for providing video BIOS functions for the computer system.

Abstract translation: 具有视频BIOS组件的接口设备。 该装置包括用于实现母板连接并实现GPU（图形处理器单元）连接的基板。 视频BIOS组件安装在基板上，用于为计算机系统提供视频BIOS功能。

公开(公告)号：US08111199B2

公开(公告)日：2012-02-07

申请号：US12958522

申请日：2010-12-02

Applicant: Carles Puente Baliarda ,  Jaime Anguera Pros

Inventor： Carles Puente Baliarda ,  Jaime Anguera Pros

IPC: H01Q1/38 ,  H01Q1/48

CPC classification number: H01Q9/0421 ,  H01Q13/10 ,  H01Q13/103 ,  H05K1/023 ,  H05K1/025 ,  H05K1/0295 ,  H05K3/222 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10636 ,  H05K2203/171 ,  H05K2203/173 ,  Y02P70/611

Abstract: A wireless device includes a ground plane with at least two portions. On each of the at least two portions at least one connecting means is provided. The two connecting means are connected with an electric component for connecting the at least two portions of the ground plane. The ground plane is partially covered with an insulating material and the connecting means are given by a part of the ground plane which is not covered by any insulating material.

Abstract translation: 无线设备包括具有至少两个部分的接地平面。 在至少两个部分中的每一个上，提供至少一个连接装置。 两个连接装置与用于连接接地平面的至少两个部分的电气部件连接。 接地平面被绝缘材料部分覆盖，连接装置由未被任何绝缘材料覆盖的接地平面的一部分给出。

公开(公告)号：US08094460B2

公开(公告)日：2012-01-10

申请号：US12352299

申请日：2009-01-12

Applicant: Brad G. Magnani ,  Raymond Eng ,  Susan M. Plul

Inventor： Brad G. Magnani ,  Raymond Eng ,  Susan M. Plul

IPC: H05K7/00

CPC classification number: H05K1/111 ,  H05K1/0295 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A land pattern, a method of manufacturing a printed circuit board (PCB) and a PCB incorporating a land pattern. In one embodiment, the land pattern includes: (1) a quadrilateral component outline area having diagonally opposed first and second corners and diagonally opposed third and fourth corners, defined according to a body configuration of a particular component type and located on a surface of a substrate and (2) first and second exposed conductive pads located within said area respectively proximate said first and second corners, coupled to respective first and second circuit conductors of said substrate, configured according to a terminal configuration of said type and separated from said third and fourth corners such that a component of said particular component type may be placed on the land pattern in multiple orientations without causing a short circuit.

Abstract translation: 地面图案，制造印刷电路板（PCB）的方法和结合了平面图案的PCB。 在一个实施例中，所述焊盘图案包括：（1）具有对角相对的第一和第二拐角以及对角相对的第三和第四角的四边形部件轮廓区域，其根据特定部件类型的主体构造而定义，并且位于 衬底和（2）位于所述区域内的第一和第二暴露的导电焊盘，分别靠近所述第一和第二拐角，耦合到所述衬底的相应的第一和第二电路导体，根据所述类型的端子配置并与所述第三和第二角分离， 第四角，使得所述特定部件类型的部件可以以多个取向放置在焊盘图案上而不引起短路。

公开(公告)号：US08059421B2

公开(公告)日：2011-11-15

申请号：US11802043

申请日：2007-05-18

Applicant: Jin-Jun Park

Inventor： Jin-Jun Park

IPC: H05K7/00

CPC classification number: H05K1/117 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0295 ,  H05K1/118 ,  H05K1/185 ,  H05K3/284 ,  H05K2201/056 ,  H05K2201/09954 ,  H05K2203/1572 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00014

Abstract: Example embodiments relate to a memory card including a generally box-shaped printed circuit board, a control chip in the generally box-shaped printed circuit board, a memory chip in the generally box-shaped printed circuit board, and a plurality of contact pads on at least two portions of an upper portion, a lower portion, a left portion and a right portion of a front face of the generally box-shaped printed circuit board, and on at least two portions of an upper portion, a lower portion, a left portion and a right portion of a rear face of the generally box-shaped printed circuit board.

Abstract translation: 示例性实施例涉及包括大体上盒形印刷电路板，大体上盒形印刷电路板中的控制芯片，大体上盒形印刷电路板中的存储芯片和多个接触垫 大致盒形印刷电路板的前表面的上部，下部，左部和右部的至少两部分，以及上部，下部， 左侧部分和大致盒形印刷电路板的后表面的右部分。