公开(公告)号：US20020076903A1

公开(公告)日：2002-06-20

申请号：US10007703

申请日：2001-12-10

Inventor： Koji Kondo ,  Tetsuaki Kamiya ,  Toshikazu Harada ,  Ryuichi Onoda ,  Yasutaka Kamiya ,  Gentaro Masuda ,  Yoshitaro Yazaki ,  Tomohiro Yokochi

IPC: H01L021/30 ,  H01L021/46 ,  H01L021/4763

CPC classification number: H05K3/4638 ,  H05K3/0035 ,  H05K3/281 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09245 ,  H05K2201/096 ,  H05K2201/09854 ,  H05K2203/063 ,  H05K2203/065 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T156/1064

Abstract: Single-sided conductor patterned films are prepared, each of which has a conductor pattern formed only one side of a resin film and via hole filled with conductive paste. A single-sided conductor patterned film which has a conductor pattern formed only one side of a resin film and an opening formed in the resin film so as to expose an electrode is laminated on the single-sided conductor patterned films. Moreover, a cover layer with an opening to expose an electrode is laminated on a bottom surface of the single-sided conductor patterned films to form a laminate. Then, by pressing while heating the laminate, a multilayer substrate having the electrodes at both sides thereof can be produced.

Abstract translation: 制备单面导体图案化膜，其每一个具有只形成树脂膜的一侧的导体图案和填充有导电浆料的通孔。 在单面导体图案化膜上层叠单面导体图案膜，其具有仅形成树脂膜的一侧的导体图案和形成在树脂膜中以露出电极的开口。 此外，在单面导体图案化膜的底面上层叠具有露出电极的开口的覆盖层，以形成层压体。 然后，通过在加热层叠体的同时按压，可以制造在其两侧具有电极的多层基板。

公开(公告)号：US06406991B2

公开(公告)日：2002-06-18

申请号：US09748022

申请日：2000-12-27

Applicant: Osamu Sugihara

Inventor： Osamu Sugihara

IPC: H01L2144

CPC classification number: H05K3/381 ,  F28F9/001 ,  F28F2265/26 ,  G01R1/06761 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/4846 ,  H01L21/4853 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/388 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2203/0733 ,  H05K2203/095 ,  Y10S438/906 ,  Y10S438/963 ,  Y10T29/49155

Abstract: In a method of manufacturing a contact element, provision is made of a laminated body which has an insulating film, an electrically conductive layer stacked on the insulating film, and bump holes opened. A treatment is carried out so as to removen organic materials and the like from an interior of the bump holes and/or a surface of the insulating film before bumps are formed on the bump holes. The treatment may be a plasma treatment or an X-ray irradiation.

Abstract translation: 在制造接触元件的方法中，提供了具有绝缘膜，层叠在绝缘膜上的导电层和打开凸块孔的层叠体。 进行处理，以便在凸点形成凸点之前从凸起孔的内部和/或绝缘膜的表面移除有机材料等。 治疗可以是等离子体治疗或X射线照射。

公开(公告)号：US06399899B1

公开(公告)日：2002-06-04

申请号：US09712980

申请日：2000-11-16

Applicant: Tadao Ohkawa ,  Yasuhito Ohwaki ,  Shigenori Morita ,  Toshihiko Omote

Inventor： Tadao Ohkawa ,  Yasuhito Ohwaki ,  Shigenori Morita ,  Toshihiko Omote

IPC: H01R1204

CPC classification number: H05K1/0271 ,  G11B5/486 ,  H01R4/023 ,  H01R13/58 ,  H01R2201/06 ,  H05K1/056 ,  H05K3/243 ,  H05K3/28 ,  H05K3/361 ,  H05K3/388 ,  H05K2201/0154 ,  H05K2201/0394

Abstract: To provide a suspension board with circuit that enables its terminals to be bonded to the other terminals with sufficient strength with simple structure, to ensure sufficient bonding reliability, the suspension board with circuit 11 includes a suspension board 12, a base layer 13 formed on the suspension board 12, and a conductive layer 14 formed on the base layer 13 and a cover layer 18 with which the conductive layer 14 is covered, wherein external connection terminals 17 to be bonded to terminals 28 of a read/write board 29 are formed without the suspension board 12 and/or the base layer 13 being formed.

Abstract translation: 为了提供具有使得其端子能够以足够的结构结合到其它端子的电路的悬挂板，为了确保足够的接合可靠性，具有电路11的悬挂板包括悬挂板12，形成在基板13上的基底层13 悬垂基板12和形成在基底层13上的导电层14和覆盖导电层14的覆盖层18，其中形成与读/写板29的端子28接合的外部连接端子17不形成 形成悬挂板12和/或基层13。

公开(公告)号：US06392429B1

公开(公告)日：2002-05-21

申请号：US09594748

申请日：2000-06-14

Applicant: David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Salman Akram

Inventor： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Salman Akram

IPC: G01R3102

CPC classification number: H01L23/49838 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2863 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/80 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/05599

Abstract: A temporary package for a semiconductor die is provided. The temporary package has an outline and external contact configuration that are the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. The package includes a base, an interconnect and a force applying mechanism. The package base includes external contacts formed in a dense array, such as a land grid array (LGA), a pin grid array (PGA), a bumped grid array (BGA) or a perimeter array. The package base can be formed of ceramic or plastic with internal conductive lines using a ceramic lamination process, a 3-D molding process or a Cerdip formation process.

Abstract translation: 提供了一种用于半导体管芯的临时封装。 临时包装具有与常规塑料或陶瓷半导体封装相同的轮廓和外部接触构造。 临时包装可用于使用标准设备对模具进行老化测试。 然后可以将模具从包装中取出并被认证为已知的好的模具。 该包装包括底座，互连和力施加机构。 封装基座包括形成在密集阵列中的外部触头，例如焊盘格栅阵列（LGA），引脚格栅阵列（PGA），凸起栅格阵列（BGA）或周边阵列。 封装基底可以由具有内部导电线的陶瓷或塑料形成，使用陶瓷层压工艺，3-D成型工艺或Cerdip形成工艺。

公开(公告)号：US20020053464A1

公开(公告)日：2002-05-09

申请号：US09955215

申请日：2001-09-18

Inventor： Chris M. Schreiber ,  Bao Le ,  Eric Dean Jensen

IPC: H01L023/02

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/49861 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/205 ,  H05K3/363 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0382 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/10757 ,  H01L2924/00

Abstract: A metallic or an electrical trace having a terminus and a stress relief bend formed in the trace adjacent the terminus. The electrical trace may have a portion carried by a flexible substrate to form a flexible circuit. The stress relief bend may be free floating and extend from the flexible substrate or may be encapsulated by the flexible substrate. The electrical circuit and the flexible circuit each have a generally planar portion extending in the X and Y axis, with the stress relief bend projecting into the Z axis. This allows electrical traces to be spaced with a very narrow pitch because the stress relief bend does not consume any valuable real estate on the flexible circuit or the substrate to which the electrical trace is applied.

Abstract translation: 在靠近终点的迹线中形成具有末端和应力消除弯曲的金属或电迹线。 电迹线可以具有由柔性基板承载的部分以形成柔性电路。 应力释放弯曲部可以是自由浮动的并且从柔性基底延伸，或者可以由柔性基底封装。 电路和柔性电路各自具有在X轴和Y轴上延伸的大致平面的部分，其中应力释放弯曲部伸入Z轴。 这允许电迹线以非常窄的间距间隔开，因为应力消除弯曲不消耗在施加电迹线的柔性电路或衬底上的任何有价值的空间。

公开(公告)号：US06381164B1

公开(公告)日：2002-04-30

申请号：US09835123

申请日：2001-04-13

Applicant: Zhineng Fan ,  Ai D. Le ,  Che-Yu Li

Inventor： Zhineng Fan ,  Ai D. Le ,  Che-Yu Li

IPC: G11C502

CPC classification number: H05K7/1061 ,  G11C5/063 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/7082 ,  H05K1/112 ,  H05K1/144 ,  H05K3/325 ,  H05K3/3436 ,  H05K2201/0314 ,  H05K2201/0394 ,  H05K2201/09845 ,  H05K2201/10378 ,  H01L2924/00

Abstract: The present invention provides a low profile, high density electronic package for high speed, high performance semiconductors, such as memory devices. It includes a plurality of modules having high speed, impedance-controlled transmission line buses, short interconnections between modules and, optionally, driver line terminators built into one of the modules, for maintaining high electrical performance. Suitable applications include microprocessor data buses and memory buses such as RAMBUS and DDR. The modules may be formed on conventional printed circuit cards with unpacked or packed memory chips attached directly to the memory module. Thermal control structures may be included to maintain the high density modules within a reliable range of operating temperatures.

Abstract translation: 本发明提供了用于高速，高性能半导体（例如存储器件）的薄型，高密度电子封装。 它包括多个模块，其具有高速，阻抗控制的传输线总线，模块之间的短互连，以及可选地，内置在模块之一中的驱动器线路终端器，用于维持高电气性能。 适用的应用包括微处理器数据总线和诸如RAMBUS和DDR之类的存储器总线。 模块可以在具有直接附接到存储器模块的未包装或打包的存储器芯片的常规印刷电路卡上形成。 可以包括热控制结构以将高密度模块保持在可靠的操作温度范围内。

公开(公告)号：US20010050566A1

公开(公告)日：2001-12-13

申请号：US09789972

申请日：2001-02-20

Inventor： Hans-Jurgen Hacke

IPC: G01R031/02

CPC classification number: G01R1/0735 ,  G01R31/2886 ,  H05K1/0393 ,  H05K1/112 ,  H05K3/326 ,  H05K2201/0394 ,  H05K2201/09472

Abstract: A printed circuit board for use in testing electrical components having distributed two-dimensional connection contacts. The printed circuit board has an electrically insulating insulation layer provided with through-holes. In the region of a respective through-hole, an electrically conductive contact pad is provided on a side surface of the insulation layer. Proceeding from a respective contact pad, a respective conductor track extends to an edge region of the insulation layer.

Abstract translation: 一种用于测试具有分布式二维连接触点的电气部件的印刷电路板。 印刷电路板具有设置有通孔的电绝缘绝缘层。 在相应通孔的区域中，导电接触垫设置在绝缘层的侧表面上。 从相应的接触垫开始，相应的导体轨道延伸到绝缘层的边缘区域。

公开(公告)号：US06330166B1

公开(公告)日：2001-12-11

申请号：US09399166

申请日：1999-09-20

Applicant: Masayuki Aoyama ,  Yasuaki Matsunaga ,  Tomoyuki Hiramatsu ,  Naoyuki Akita ,  Koji Kondo

Inventor： Masayuki Aoyama ,  Yasuaki Matsunaga ,  Tomoyuki Hiramatsu ,  Naoyuki Akita ,  Koji Kondo

IPC: H05K702

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3452 ,  H05K2201/0394 ,  H05K2201/09427 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2203/0465 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In an electronic-component mounting structure, an electronic component (2) has a surface. First electrodes (1) provided on the surface of the electronic component (2) are arranged in a first array. Second electrodes (3) provided on a base board (4) are arranged in a second array corresponding to the first array. The second electrodes (3) correspond to the first electrodes (1) respectively. Solder bumps (9) connect the first electrodes (1) and the second electrodes (3) respectively. The first electrodes (1) include first outermost electrodes (1b) located in an outer area of the first array. The second electrodes (3) include second outermost electrodes (3b, 3c) located in an outer area of the second array. The second outermost electrodes (3b, 3c) correspond to the first outermost electrodes (1b) respectively. An outer edge (X1, Z1) of each of the second outermost electrodes (3b, 3c) extends outward of an outer edge (Y1) of a corresponding first outermost electrode (1b) with respect to the first and second arrays. A distance between an outer edge (X1, Z1) of each of the second outermost electrodes (3b, 3c) and an outer edge (Y1) of a corresponding first outermost electrode (1b) is greater than a distance between an inner edge (X2, Z2) of the second outermost electrode (3b, 3c) and an inner edge (Y2) of the corresponding first outermost electrode (1b) with respect to the first and second arrays.

Abstract translation: 在电子部件安装结构中，电子部件（2）具有表面。 设置在电子部件（2）的表面上的第一电极（1）以第一阵列布置。 设置在基板（4）上的第二电极（3）以对应于第一阵列的第二阵列布置。 第二电极（3）分别对应于第一电极（1）。 焊接凸块（9）分别连接第一电极（1）和第二电极（3）。 第一电极（1）包括位于第一阵列的外部区域中的第一最外电极（1b）。 第二电极（3）包括位于第二阵列的外部区域中的第二最外电极（3b，3c）。 第二最外电极（3b，3c）分别对应于第一最外电极（1b）。 每个第二最外电极（3b，3c）的外边缘（X1，Z1）相对于第一和第二阵列延伸到对应的第一最外电极（1b）的外边缘（Y1）的外侧。 每个第二最外电极（3b，3c）的外边缘（X1，Z1）与对应的第一最外电极（1b）的外边缘（Y1）之间的距离大于内边缘（X2 ，Z2）和相应的第一最外电极（1b）的内边缘（Y2）相对于第一和第二阵列。

公开(公告)号：US06320397B1

公开(公告)日：2001-11-20

申请号：US08614735

申请日：1996-03-13

Applicant: Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree

Inventor： Alan G. Wood ,  Warren M. Farnworth ,  David R. Hembree

IPC: G01R1073

CPC classification number: G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/75 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/75 ,  H01L2224/85001 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49172 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A carrier for testing an unpackaged semiconductor die is provided. The carrier includes a carrier base for supporting the die; an interconnect for establishing a temporary electrical connection with the die; and a force distribution mechanism for biasing the die and interconnect together. In an illustrative embodiment the carrier is formed with a laminated ceramic base. The ceramic base includes internal conductive lines that are wire bonded to the interconnect and metal plated external contacts that are connected to external test circuitry. In an alternate embodiment the carrier is formed with an injection molded plastic base and includes 3-D circuitry formed by a metallization and photolithographic process. In either case, the carrier is adapted for testing different die configurations by interchanging different interconnects.

Abstract translation: 提供了用于测试未封装的半导体管芯的载体。 载体包括用于支撑模具的载体基体; 用于建立与所述管芯的临时电连接的互连; 以及用于偏压模具并互连在一起的力分配机构。 在说明性实施例中，载体形成有层压陶瓷基底。 陶瓷基座包括内部导电线，引线连接到互连线和金属电镀外部触点，连接到外部测试电路。 在替代实施例中，载体由注射成型的塑料基底形成，并且包括通过金属化和光刻工艺形成的3-D电路。 在任一情况下，载体适于通过互换不同的互连来测试不同的管芯配置。

公开(公告)号：US20010028104A1

公开(公告)日：2001-10-11

申请号：US09769394

申请日：2001-01-26

Inventor： Kenta Fukatsu ,  Yasuhito Saito ,  Masayuki Arakawa ,  Tomohiro Iguchi ,  Naotake Watanabe ,  Yoshitoshi Fukuchi ,  Tetsuro Komatsu

IPC: H01L021/44 ,  H01L021/48 ,  H01L023/02 ,  H01L023/48 ,  H01L029/40

CPC classification number: H05K3/363 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/144 ,  H05K3/3442 ,  H05K2201/0394 ,  H05K2201/09181 ,  H05K2201/096 ,  H05K2201/0969 ,  H05K2201/10681

Abstract: In a stacked-type semiconductor unit having a plurality of semiconductor devices stacked on a base board including a base electrode, each semiconductor device has a wiring board including an external electrode provided in an end portion thereof. The semiconductor devices are stacked on the base board such that the external electrodes are aligned with one another. Then, the external electrodes are electrically connected to the base board by solder.

Abstract translation: 在具有堆叠在包括基极的基板上的多个半导体器件的叠层型半导体单元中，每个半导体器件具有包括设置在其端部中的外部电极的布线板。 半导体器件堆叠在基板上，使得外部电极彼此对准。 然后，外部电极通过焊料与基板电连接。