公开(公告)号：US20040137659A1

公开(公告)日：2004-07-15

申请号：US10604650

申请日：2003-08-07

Inventor： Yi-Chuan Ding ,  Yung-I Yeh

IPC: H01L021/48

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/285 ,  H05K3/4644 ,  H05K3/4676 ,  H05K2201/068 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A substrate includes a dielectric structure, an interconnection structure and a solder mask. The interconnection structure interlaces inside the dielectric structure. The solder mask covers the dielectric structure. The material of the solder mask can be the same as that of the dielectric structure contacting the solder mask. The material of the solder mask can be epoxy resin or bismaleimide-triazine.

Abstract translation: 基板包括电介质结构，互连结构和焊接掩模。 互连结构在电介质结构内部交织。 焊接掩模覆盖电介质结构。 焊料掩模的材料可以与接触焊料掩模的电介质结构的材料相同。 焊料掩模的材料可以是环氧树脂或双马来酰亚胺三嗪。

公开(公告)号：US20040067349A1

公开(公告)日：2004-04-08

申请号：US10467463

申请日：2003-11-17

Inventor： Kazuto Okamura ,  Kazutoshi Taguchi ,  Kazunori Ohmizo ,  Makoto Shimose

IPC: B32B003/00

CPC classification number: B32B15/08 ,  B32B27/06 ,  B32B27/18 ,  B32B27/36 ,  H05K1/0346 ,  H05K1/036 ,  H05K3/002 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2203/0759 ,  Y10T428/24917 ,  Y10T428/24942 ,  Y10T428/2495 ,  Y10T428/24959 ,  Y10T428/31681 ,  Y10T428/31721

Abstract: This invention relates to a laminate comprising an insulating polyimide resin layer etchable by an aqueous alkaline solution and a metal foil. The laminate has an insulating resin layer composed of a plurality of polyimide resin layers on the metal foil and the insulating resin layer has at least one polyimide resin layer (A) with a coefficient of linear thermal expansion (CTE) of 30null10null6/null C. or less and at least one polyimide resin layer (B) with a glass transition temperature (Tg) of 300null C. or below, the layer in contact with the metal foil is the polyimide resin layer (B), the bonding strength between the metal foil and the polyimide resin layer (B) in contact therewith is 0.5 kN/m or more, and the average rate of etching of the insulating resin layer by a 50 wt % aqueous solution of potassium hydroxide at 80null C. is 0.5 nullm/min or more. The laminate is useful for flexible printed circuits and the like.

Abstract translation: 本发明涉及包含可由碱性水溶液和金属箔蚀刻的绝缘聚酰亚胺树脂层的层压体。 层压体具有在金属箔上由多个聚酰亚胺树脂层构成的绝缘树脂层，绝缘树脂层具有至少一个线性热膨胀系数（CTE）为30×10 -6的聚酰亚胺树脂层（A） /℃以下的玻璃化转变温度（Tg）为300℃以下的聚酰亚胺树脂层（B），与金属箔接触的层为聚酰亚胺树脂层（B）， 金属箔和与其接触的聚酰亚胺树脂层（B）之间的接合强度为0.5kN / m以上，通过50重量％氢氧化钾水溶液在80℃下的绝缘树脂层的平均蚀刻速度 为0.5m / min以上。 该层压板可用于柔性印刷电路等。

公开(公告)号：US06703262B2

公开(公告)日：2004-03-09

申请号：US09195514

申请日：1998-11-19

Applicant: Minehiro Itagaki ,  Yoshihiro Tomuro ,  Satoru Yuhaku ,  Kazuyoshi Amami

Inventor： Minehiro Itagaki ,  Yoshihiro Tomuro ,  Satoru Yuhaku ,  Kazuyoshi Amami

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K3/0011 ,  H05K3/007 ,  H05K3/386 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2203/016 ,  H05K2203/0278 ,  H05K2203/1105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.

公开(公告)号：US06669489B1

公开(公告)日：2003-12-30

申请号：US09107924

申请日：1998-06-30

Applicant: Thomas H. Dozier, II ,  Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu

Inventor： Thomas H. Dozier, II ,  Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu

IPC: H01R1200

CPC classification number: B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/0483 ,  G01R1/06711 ,  G01R1/07314 ,  G01R1/07357 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4015 ,  H05K3/4092 ,  H05K7/1069 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48

Abstract: Surface-mount, solder-down sockets permit electronic components such as semiconductor packages to be releasably mounted to a circuit board or other electronic component. In an embodiment, resilient contact structures extend through a support substrate, and solder-ball (or other suitable) contact structures are disposed along the bottom of the support substrate in electrical contact with the ends of the resilient contact structures. Composite interconnection elements are used as the resilient contact structures disposed atop the support substrate. In an embodiment intended to receive an LGA-type semiconductor package, pressure contact is made between the resilient contact structures and external connection points of the semiconductor package with a contact force which is generally normal to the top surface of the support substrate. In an embodiment intended to receive a BGA-type semiconductor package, pressure contact is made between the resilient contact structures and external connection points of the semiconductor package with a contact force which is generally parallel to the top surface of the support substrate.

Abstract translation: 表面贴装焊接插座允许诸如半导体封装的电子部件可释放地安装到电路板或其他电子部件。 在一个实施例中，弹性接触结构延伸穿过支撑衬底，并且焊球（或其它合适的）接触结构沿着与弹性接触结构的端部电接触的支撑衬底的底部设置。 复合互连元件用作设置在支撑基板上的弹性接触结构。 在旨在接收LGA型半导体封装的实施例中，弹性接触结构与半导体封装的外部连接点之间的压力接触，其接触力通常垂直于支撑衬底的顶表面。 在旨在接收BGA型半导体封装的实施例中，在弹性接触结构和半导体封装的外部连接点之间以大体平行于支撑衬底的顶表面的接触力进行压力接触。

公开(公告)号：US20030218871A1

公开(公告)日：2003-11-27

申请号：US10445000

申请日：2003-05-27

Inventor： Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

IPC: H01L021/00

CPC classification number: H05K3/44 ,  H05K1/115 ,  H05K3/4641 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: A multilayer circuit board having a high level of reliability in terms of electric connection against temperature changes caused by the actual operation of electronic equipment, a manufacturing process, a substrate for multilayer circuitry, and an electronic apparatus. The multilayer circuit board comprises a laminate of at least one insulating layer and at least one wiring layer, wherein the wiring layer is formed by a composite member comprising a first metal layer and a second metal layer formed on one or both sides of the first metal layer, the first metal layer having a smaller coefficient of thermal expansion than the second metal layer, the second metal layer having a higher electric conductivity than the first metal layer, wherein the insulating layer has a blind via-hole with a bottom provided by a surface of the second metal layer, the circuit board further comprising a layer-to-layer interconnection portion on the surface of the insulating layer and in the blind via-hole, wherein the layer-to-layer interconnection portion in the blind via-hole is formed in such a manner as to be in contact with the surface of the second metal layer.

Abstract translation: 一种多层电路板，其具有与由电子设备的实际操作，制造工艺，多层电路的基板和电子设备引起的温度变化的电连接方面的高可靠性。 所述多层电路板包括至少一层绝缘层和至少一层布线层的叠层体，其中所述布线层由复合构件形成，所述复合构件包括形成在所述第一金属的一侧或两侧上的第一金属层和第二金属层 所述第一金属层具有比所述第二金属层更小的热膨胀系数，所述第二金属层具有比所述第一金属层更高的导电性，其中所述绝缘层具有盲孔，所述盲通孔具有由 第二金属层的表面，电路板还包括在绝缘层的表面和盲孔中的层间互连部分，其中盲通孔中的层间互连部分 形成为与第二金属层的表面接触的方式。

公开(公告)号：US06642282B2

公开(公告)日：2003-11-04

申请号：US10103886

申请日：2002-03-25

Applicant: Yasuo Shinohara ,  Tsutomu Takahashi

Inventor： Yasuo Shinohara ,  Tsutomu Takahashi

IPC: C08J900

CPC classification number: C08J5/18 ,  C08J9/0061 ,  C08J9/28 ,  C08J2201/0544 ,  C08J2377/08 ,  C08J2477/00 ,  C08L67/03 ,  C08L77/08 ,  C08L77/10 ,  C08L79/06 ,  C08L79/08 ,  H05K1/0346 ,  H05K1/0366 ,  H05K1/0373 ,  H05K2201/0116 ,  H05K2201/0129 ,  H05K2201/0212 ,  H05K2201/068 ,  C08L77/00

Abstract: Provided is a porous para-oriented aromatic polyamide film which contains fine particles composed of a heat-resistant resin in an amount of 10 to 400 parts by weight based on 100 parts by weight of a pare-oriented aromatic polyamide and has a linear thermal expansion coefficient at 200 to 300° C. of from −50×10−6/° C. to +50×10−6/° C. The porous para-oriented aromatic polyamide film shows excellent tear propagation resistance and has light weight and low linear thermal expansion coefficient, and is suitable as a prepreg material used for a base substrate for printed circuit board.

Abstract translation: 本发明提供一种多孔对位芳香族聚酰胺薄膜，其包含由100重量份的取向芳香族聚酰胺构成的10〜400重量份的由耐热性树脂构成的微粒子，并具有线性热膨胀 200〜300℃的系数为-50×10 -6 /℃至+ 50×10 -6 /℃。多孔对位芳族聚酰胺膜显示出优异的抗撕裂传播性，重量轻且低 线性热膨胀系数，并且适合作为用于印刷电路板的基底的预浸料材料。

公开(公告)号：US06639155B1

公开(公告)日：2003-10-28

申请号：US08872782

申请日：1997-06-11

Applicant: James R. Bupp ,  Donald S. Farquhar ,  Lisa J. Jimarez

Inventor： James R. Bupp ,  Donald S. Farquhar ,  Lisa J. Jimarez

IPC: H05K116

CPC classification number: H05K3/4688 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/015 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0376 ,  H05K2201/068

Abstract: A packaging platform for interconnecting integrated circuit chips and cards, in which the platform is a circuitized fluoropolymer-based laminate carrier including high purity fluoropolymer protective barriers on its surfaces.

Abstract translation: 用于互连集成电路芯片和卡的封装平台，其中该平台是在其表面上包括高纯度氟聚合物保护屏障的基于含氟聚合物的电路层叠载体。

公开(公告)号：US20030122570A1

公开(公告)日：2003-07-03

申请号：US10327468

申请日：2002-12-20

Inventor： Phillip E. Byrd

IPC: G01R031/26 ,  G01R031/02

CPC classification number: G01R1/06766 ,  G01R1/07371 ,  G01R3/00 ,  G01R31/2886 ,  H05K1/0293 ,  H05K1/09 ,  H05K1/167 ,  H05K2201/068 ,  H05K2201/10053 ,  H05K2201/10181 ,  Y10T29/49004 ,  Y10T29/49005 ,  Y10T29/49107 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204

Abstract: A method for probe cards configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. In embodiments of the invention, protective fuses are provided in electrical communication with conductive traces and probe elements (e.g., probe needles) of a probe card. The fuses may be active or passive fuses and are preferably self-resetting, repairable, and/or replaceable. Typically, the fuses will be interposed in, or located adjacent to, conductive traces residing over a surface of the probe card. In this regard, methods of fabricating a probe card are provided, as well as various probe card configurations. A semiconductor die testing system using the probe card of the present invention is also provided.

Abstract translation: 一种用于探针卡的方法，其配置有适用于半导体裸片的电测试而不损坏探针卡的保护电路。 在本发明的实施例中，提供了与探针卡的导电迹线和探针元件（例如，探针）电连通的保护性熔丝。 保险丝可以是有源或被动保险丝，并且优选地是自复位，可修复和/或可更换的。 通常，保险丝将被置于位于探针卡的表面上方的导电迹线中或邻近其上。 在这方面，提供了制造探针卡的方法以及各种探针卡配置。 还提供了使用本发明的探针卡的半导体管芯测试系统。

公开(公告)号：US20030122564A1

公开(公告)日：2003-07-03

申请号：US10327246

申请日：2002-12-20

Inventor： Phillip E. Byrd

IPC: G01R031/02

CPC classification number: G01R1/06766 ,  G01R1/07371 ,  G01R3/00 ,  G01R31/2886 ,  H05K1/0293 ,  H05K1/09 ,  H05K1/167 ,  H05K2201/068 ,  H05K2201/10053 ,  H05K2201/10181 ,  Y10T29/49004 ,  Y10T29/49005 ,  Y10T29/49107 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204

Abstract: Probe cards configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. In embodiments of the invention, protective fuses are provided in electrical communication with conductive traces and probe elements (e.g., probe needles) of a probe card. The fuses may be active or passive fuses and are preferably self-resetting, repairable, and/or replaceable. Typically, the fuses will be interposed in, or located adjacent to, conductive traces residing over a surface of the probe card. In this regard, methods of fabricating a probe card are provided, as well as various probe card configurations. A semiconductor die testing system using the probe card of the present invention is also provided.

公开(公告)号：US20030102156A1

公开(公告)日：2003-06-05

申请号：US09998348

申请日：2001-11-30

Inventor： Richard K. Spielberger ,  Ronald J. Jensen ,  Thomas G. Wagner

IPC: H05K001/16

CPC classification number: H05K3/3436 ,  H01L2224/48091 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K1/141 ,  H05K2201/068 ,  H05K2201/10378 ,  Y02P70/613 ,  H01L2924/00014

Abstract: A ball grid array mounted circuit includes a stress relief substrate having spaced conductive vias extending between its surfaces and connection pads at the surfaces. Solder connections formed from solder balls connect between pads at the top surface and connection pads at an electronic component. Solder connections formed from solder balls connect between pads at the bottom surface and connection pads at a printed circuit board (PCB). The solder connections absorb at least a portion of the stress due to differences between the thermal coefficient of expansion of the electronic component and the PCB.

Abstract translation: 球栅阵列安装电路包括应力消除基板，其具有在其表面之间延伸的间隔的导电通孔和在表面处的连接焊盘。 由焊球形成的焊接连接在顶表面的焊盘和电子部件的连接焊盘之间。 由焊球形成的焊接连接在底面的焊盘和印刷电路板（PCB）的连接焊盘之间。 由于电子部件的热膨胀系数与PCB之间的差异，焊料连接物吸收至少一部分应力。