公开(公告)号：US09287635B2

公开(公告)日：2016-03-15

申请号：US14690569

申请日：2015-04-20

Applicant: Panduit Corp.

Inventor： Jack E. Caveney ,  Scott M. Lesniak

IPC: H01R24/64 ,  H01R4/24 ,  H05K1/02 ,  H01R13/6466 ,  H01R13/6469 ,  H01R13/66 ,  H05K1/16

CPC classification number: H01R4/2416 ,  H01R4/2433 ,  H01R13/6466 ,  H01R13/6469 ,  H01R13/665 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10S439/942 ,  Y10T29/49201 ,  Y10T29/49202 ,  Y10T29/49204 ,  Y10T29/49208

Abstract: A network cable jack includes a printed circuit board (PCB) for balancing both inductive and capacitive coupling. Using a PCB allows compact trace paths to be formed without significantly increasing manufacturing costs. By including on each trace path two distinct inductance zones separated by a neutral zone, significant gains in degrees of freedom are achieved for designing PCB trace patterns in which a pair of inductive coupling zones jointly offset the inductive coupling caused by a specification plug and the jack contacts, both in magnitude and phase angle. Further, using distinct inductance zones offers more freedom regarding the placement of capacitive plates for use in capacitance balancing as well as the placement of terminals and insulation displacement contacts. Although the magnitude of a capacitive coupling is determined by the length of the capacitor plates parallel to current carrying traces, the approach allows capacitive and inductive coupling to be balanced independently.

公开(公告)号：USRE45885E1

公开(公告)日：2016-02-09

申请号：US14260240

申请日：2014-04-23

Applicant: Plastic Logic Limited

Inventor： Paul A. Cain ,  Carl Hayton

IPC: H01L21/00 ,  H01L21/461 ,  H01L51/00 ,  B23K26/06 ,  B23K26/40 ,  H05K3/02 ,  H01L21/268 ,  H01L21/768 ,  H05K3/46

CPC classification number: H01L51/0023 ,  B23K26/063 ,  B23K26/4075 ,  B23K2101/40 ,  B23K2103/16 ,  H01L21/268 ,  H01L21/76838 ,  H05K3/027 ,  H05K3/4644 ,  H05K2201/09672

Abstract: A method of fabricating an electronic device, the device including a plurality of layers on a substrate, the layers including an upper conductive layer and at least one patterned underlying layer between said conductive layer and said substrate. The method includes patterning said underlying layer, and patterning said upper conductive layer by laser ablation using a stepwise process in which successive areas of said upper conductive layer are ablated by successively applied laser patterns. The successively applied laser patterns overlap one another in an overlap region. The method further includes configuring a said laser pattern and said patterned underlying layer with respect to one another such that in a said overlap region said patterned underlying layer is substantially undamaged by said stepwise laser ablation.

Abstract translation: 一种制造电子器件的方法，所述器件在衬底上包括多个层，所述层包括上导电层和在所述导电层和所述衬底之间的至少一个图案化底层。 该方法包括图案化所述下层，以及通过使用逐步过程的激光烧蚀来图案化所述上导电层，其中所述上导电层的连续区域被依次施加的激光图案消融。 连续施加的激光图案在重叠区域中彼此重叠。 该方法还包括相对于彼此配置所述激光图案和所述图案化的下层，使得在所述重叠区域中，所述图案化下层通过所述逐步激光烧蚀基本上未损坏。

公开(公告)号：US09246274B2

公开(公告)日：2016-01-26

申请号：US14215817

申请日：2014-03-17

Applicant: Panduit Corp.

Inventor： Joshua A. Valenti ,  Moulik Shah ,  Ronald L. Tellas ,  Robert E. Fransen ,  Satish I. Patel ,  Tse-Yu Lin

IPC: H01R13/6466 ,  H01R24/64 ,  H05K1/02 ,  H05K1/16

CPC classification number: H01R13/6466 ,  H01R24/64 ,  H01R2201/04 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  H05K2201/10303

Abstract: The present invention generally relates to the field of network communications, and more specifically to networks for crosstalk reduction/compensation and communication connectors which employ such networks. In an embodiment, the present invention is an RJ45 jack with an orthogonal compensation network to meet CAT6A or higher performance standard. For the 3:6-4:5 wire-pair combination, the orthogonal compensation network begins in the jack nose (plug interface contact (PIC)) section, and utilizes a flexible printed circuit board in the nose section, split PIC contacts in the rear nose, and circuitry in the rigid printed circuit board to create the orthogonal compensation network.

Abstract translation: 本发明一般涉及网络通信领域，更具体地涉及使用这种网络的用于串扰减少/补偿和通信连接器的网络。 在一个实施例中，本发明是具有正交补偿网络以满足CAT6A或更​​高性能标准的RJ45插座。 对于3：6-4：5线对组合，正交补偿网络从插孔（插头接口触点（PIC））部分开始，并在鼻部使用柔性印刷电路板，将PIC触点 后鼻和刚性印刷电路板中的电路，以创建正交补偿网络。

公开(公告)号：US20150270241A1

公开(公告)日：2015-09-24

申请号：US14667490

申请日：2015-03-24

Applicant: Efficient Power Conversion Corporation

Inventor： ROBERT STRITTMATTER ,  Seshadri Kolluri ,  Robert Beach ,  Jianjun Cao ,  Alana Nakata

IPC: H01L23/00 ,  B23K1/00

CPC classification number: H01L24/81 ,  B23K1/0004 ,  B23K1/0016 ,  B23K3/047 ,  B23K3/0623 ,  B23K2101/42 ,  H01L23/4824 ,  H01L23/49844 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/16227 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/32227 ,  H01L2224/8112 ,  H01L2224/81234 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/8312 ,  H01L2224/83234 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2924/1306 ,  H01L2924/1461 ,  H05K1/0265 ,  H05K2201/09672 ,  H05K2201/10166 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.

Abstract translation: 一种用于将半导体器件与倒装芯片形状电连接到印刷电路板的方法和系统。 该方法的示例性实施例包括：将器件上的焊接触点与外部电路的第一铜触点和第二铜触点对准，并且仅将电源电流直接施加到第一铜的掩埋层，而不是直接连接到 层，其最接近设备，使得没有电流通过最靠近设备的层来源到设备。

公开(公告)号：US09136212B2

公开(公告)日：2015-09-15

申请号：US13247031

申请日：2011-09-28

Applicant: Noboru Kato

Inventor： Noboru Kato

IPC: H05K1/00 ,  H01L23/498 ,  H05K1/02 ,  H05K1/14 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/115 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/141 ,  H05K1/16 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0352 ,  H05K2201/09672 ,  H05K2201/10674 ,  H01L2224/05599

Abstract: A circuit board includes a laminated body including a laminate of a plurality of insulating-material layers made of a flexible material. External electrodes are provided on the top surface of the laminated body. An electronic component is mounted on the external electrodes. A plurality of internal conductors, when viewed in plan in the z-axis direction, are overlaid on the external electrodes and are not connected to one another in regions in which the internal conductors are overlaid on the external electrodes.

Abstract translation: 电路板包括层压体，其包括由柔性材料制成的多个绝缘材料层的层叠体。 外部电极设置在层压体的顶表面上。 电子部件安装在外部电极上。 当沿着z轴方向平面地观察时，多个内部导体重叠在外部电极上，并且在内部导体重叠在外部电极上的区域中彼此不连接。

公开(公告)号：US09131602B2

公开(公告)日：2015-09-08

申请号：US13747738

申请日：2013-01-23

Applicant: MediaTek Inc.

Inventor： Sheng-Ming Chang ,  Shih-Chieh Lin ,  Nan-Cheng Chen

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0219 ,  H05K1/0218 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/114 ,  H05K1/115 ,  H05K2201/0723 ,  H05K2201/09672 ,  H05K2201/09709 ,  H05K2201/10522 ,  H05K2201/10674

Abstract: The invention provides a printed circuit board for mobile platforms. An exemplary embodiment of the printed circuit board for mobile platforms includes a core substrate having a first side. A ground plane covers the first side. A first insulating layer covers the ground plane. A plurality of first signal traces and a plurality of first ground traces are alternatively arranged on the first insulating layer. A second insulating layer connects to the first insulating layer. A plurality of second signal traces separated from each other is disposed on the second insulating layer, wherein the second signal traces are disposed directly on spaces between the first signal traces and the first ground traces adjacent thereto.

Abstract translation: 本发明提供一种用于移动平台的印刷电路板。 用于移动平台的印刷电路板的示例性实施例包括具有第一侧的芯基板。 地平面覆盖第一面。 第一绝缘层覆盖接地层。 多个第一信号迹线和多个第一接地迹线交替地布置在第一绝缘层上。 第二绝缘层连接到第一绝缘层。 彼此分离的多个第二信号迹线设置在第二绝缘层上，其中第二信号迹线直接设置在第一信号迹线和与其相邻的第一接地迹线之间的空间上。

公开(公告)号：US20150228706A1

公开(公告)日：2015-08-13

申请号：US14490467

申请日：2014-09-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hee-Kwon Lee

IPC: H01L27/32 ,  G02F1/1368 ,  G02F1/1335 ,  H05K1/02 ,  H05K1/11

CPC classification number: G02F1/1368 ,  G02F1/13452 ,  H01L27/3241 ,  H01L27/3244 ,  H05K1/0245 ,  H05K1/117 ,  H05K1/189 ,  H05K2201/09409 ,  H05K2201/09481 ,  H05K2201/09672 ,  H05K2201/09781 ,  H05K2201/10128

Abstract: A display device according to an example embodiment of the present invention includes a display panel configured to display an image, the display panel including a plurality of pixels, a chip on film (COF) coupled to the display panel, the COF comprising a driver, a plurality of COF wires and a plurality of COF pads, and a flexible printed circuit board (FPCB) coupled to the COF, the FPCB including a plurality of FPCB wires and a plurality of FPCB pads, wherein the plurality of COF pads are arranged in two rows, and wherein one or more COF pads of the plurality of COF pads in a first row of the two rows are one or more dummy pads.

Abstract translation: 根据本发明的示例性实施例的显示装置包括被配置为显示图像的显示面板，包括多个像素的显示面板，耦合到显示面板的薄膜（COF），包括驱动器的COF， 多个COF线和多个COF垫，以及耦合到COF的柔性印刷电路板（FPCB），所述FPCB包括多个FPCB布线和多个FPCB垫，其中所述多个COF垫布置在 两排，并且其中两行中的第一行中的多个COF焊盘中的一个或多个COF焊盘是一个或多个虚拟焊盘。

公开(公告)号：US20150179334A1

公开(公告)日：2015-06-25

申请号：US14288877

申请日：2014-05-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Nak Jun JEONG ,  Jong Woo Kim ,  Sung Yun Han ,  Heung Gyoon Choi ,  Seung Hwan Lee ,  Young Seung Noh ,  Geun Young Park

IPC: H01F27/36 ,  H05K1/18 ,  H01F27/28

CPC classification number: H01F27/2885 ,  H01F27/28 ,  H01F27/2804 ,  H01F27/2823 ,  H01F27/362 ,  H01F2027/2809 ,  H05K1/0224 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/086 ,  H05K2201/09672 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10522 ,  H05K2203/1476

Abstract: A transformer may include: a primary coil part including a plurality of substrates on which coil patterns are formed; a secondary coil part including an insulated coil; and a shielding part formed on the primary coil part and including one or more substrates on which a shielding pattern is formed.

Abstract translation: 变压器可以包括：初级线圈部分，其包括形成有线圈图案的多个基板; 包括绝缘线圈的次级线圈部分; 以及形成在初级线圈部上并且包括一个或多个衬底的屏蔽部件，在其上形成有屏蔽图案。

公开(公告)号：US09060420B2

公开(公告)日：2015-06-16

申请号：US13118545

申请日：2011-05-30

Applicant: Dennis W. Hogg

Inventor： Dennis W. Hogg

IPC: H05K3/06 ,  H05K3/10 ,  G11B5/48 ,  H05K3/00 ,  H05K3/04 ,  H05K3/18

CPC classification number: H05K3/0082 ,  G11B5/486 ,  H05K3/048 ,  H05K3/06 ,  H05K3/184 ,  H05K2201/0108 ,  H05K2201/09672 ,  H05K2203/0551 ,  Y10T29/49025 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of manufacturing a flex circuit is disclosed for a disk drive comprising a disk, a head actuated radially over the disk, and control circuitry. The flex circuit is for electrically coupling the head to the control circuitry and comprises a substrate. An electrical coating applied to a first side of the substrate is etched to form a first electrical lead. The first side of the substrate is irradiated with radiation such that the first electrical lead masks the radiation from passing through the substrate to prevent curing of a photoresist applied to the second side of the substrate to form an uncured photoresist and a cured photoresist on the second side of the substrate. The uncured photoresist is removed from the second side of the substrate to form a groove, and the groove is filled with electrically conductive material to form the second electrical lead.

Abstract translation: 公开了一种用于磁盘驱动器的磁盘驱动器的制造方法，所述磁盘驱动器包括盘，在盘上径向驱动的磁头和控制电路。 柔性电路用于将磁头电耦合到控制电路并且包括基板。 施加到基板的第一侧的电涂层被蚀刻以形成第一电引线。 用辐射照射衬底的第一侧，使得第一电引线掩蔽穿过衬底的辐射，以防止施加到衬底的第二侧的光致抗蚀剂的固化，以形成未固化的光致抗蚀剂和在第二层上固化的光致抗蚀剂 侧面。 将未固化的光致抗蚀剂从衬底的第二侧移除以形成凹槽，并且用导电材料填充凹槽以形成第二电引线。

公开(公告)号：US20150163917A1

公开(公告)日：2015-06-11

申请号：US14621459

申请日：2015-02-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kuniaki YOSUI

IPC: H05K1/18 ,  H05K3/46 ,  H05K3/10 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/183 ,  H01L2224/16227 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0306 ,  H05K1/181 ,  H05K1/185 ,  H05K3/10 ,  H05K3/366 ,  H05K3/4623 ,  H05K3/4635 ,  H05K3/4644 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10098 ,  H05K2203/06 ,  Y10T29/49155

Abstract: A circuit board includes a main portion obtained by stacking a plurality of base sheets made of a flexible material in a predetermined direction and bonding the base sheets under pressure, and at least one planar conductor pattern provided in the main portion and including a concave portion and a convex portion. The concave portion and the convex portion extend in a direction perpendicular or substantially perpendicular to the predetermined direction. The concave portion is sunken in a direction parallel or substantially parallel to the predetermined direction. The convex portion protrudes in an opposite direction to the direction in which the concave portion is sunken. The at least one planar conductor pattern includes a first planar conductor pattern with a concave portion and a convex portion extending in a first direction. The circuit board further includes a plurality of first auxiliary members provided on one principal surface of the first planar conductor pattern and extending in the first direction, the first auxiliary members being spaced apart in a third direction different from the first direction.

Abstract translation: 电路板包括主要部分，其通过在预定方向上堆叠由柔性材料制成的多个基片并且在压力下粘合基片而获得，并且至少一个平面导体图案设置在主体部分中并且包括凹部和 凸部。 凹部和凸部沿与预定方向垂直或大致垂直的方向延伸。 凹部在与规定方向平行或大致平行的方向凹陷。 凸部沿与凹部凹陷的方向相反的方向突出。 所述至少一个平面导体图案包括具有凹部的第一平面导体图案和在第一方向上延伸的凸部。 电路板还包括设置在第一平面导体图案的一个主表面上并沿第一方向延伸的多个第一辅助构件，第一辅助构件在与第一方向不同的第三方向上间隔开。