公开(公告)号：US20040239420A1

公开(公告)日：2004-12-02

申请号：US10807244

申请日：2004-03-24

Inventor： Yuta Araki ,  Hiroyuki Kayano ,  Keiichi Yamaguchi

IPC: H03F003/68

CPC classification number: H03F1/0277 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/429 ,  H05K1/0265 ,  H05K1/165 ,  H05K2201/09254 ,  H05K2201/09263

Abstract: A power amplifier includes amplifier elements to amplify input signals of different frequencies. The amplifier also includes a power supply circuit that includes a common power supply path including an end connected to a power supply input terminal connected to a DC power supply. The amplifier further includes individual power supply paths each including an end connected to the other end of the common power supply path, and the other end connected to the main electrode of a corresponding one of the amplifier elements. The individual power supply paths have different impedances.

Abstract translation: 功率放大器包括用于放大不同频率的输入信号的放大器元件。 放大器还包括电源电路，其包括公共电源路径，其包括连接到连接到DC电源的电源输入端的端部。 放大器还包括单独的电源路径，每个电源路径包括连接到公共电源路径的另一端的端部，另一端连接到相应的一个放大器元件的主电极。 各个电源路径具有不同的阻抗。

公开(公告)号：US06771515B2

公开(公告)日：2004-08-03

申请号：US09970442

申请日：2001-10-04

Applicant: James A. McCall ,  Hing Y. To

Inventor： James A. McCall ,  Hing Y. To

IPC: H05K706

CPC classification number: H05K1/0246 ,  G11C5/063 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022

Abstract: In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extends from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module. The first path couples to chips of the first and second modules, and each of the chips include on die terminations, but only some of the chips include on die terminations that are enabled.

Abstract translation: 在一些实施例中，本发明包括具有第一和第二模块的系统以及包括分别用于接收第一和第二模块的第一和第二模块连接器的电路板。 导体的第一路径从电路板延伸到第一模块连接器，第一模块，第一模块连接器，电路板，第二模块连接器和第二模块。 第一路径耦合到第一和第二模块的芯片，并且每个芯片包括芯片端子，但是仅一些芯片包括能够启用的芯片端子。

公开(公告)号：US20030210113A1

公开(公告)日：2003-11-13

申请号：US10455454

申请日：2003-06-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Seiji Hidaka ,  Michiaki Ota ,  Shin Abe

IPC: H01P003/08 ,  H01P001/203

CPC classification number: H01P3/081 ,  H01P1/203 ,  H01P1/2039 ,  H01P7/082 ,  H05K1/0239 ,  H05K1/0242 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09781

Abstract: A transmission line, a resonator, a filter, a duplexer, and a communication apparatus efficiently minimize power losses due to edge effects, thereby having superior loss-reduction characteristics. A continuous line and a plurality of thin lines each having a predetermined length and branching from both sides of the continuous line are formed on a dielectric substrate. With this structure, edges of the individual thin lines substantially do not exist, so that losses due to edge effects can be efficiently minimized.

Abstract translation: 传输线，谐振器，滤波器，双工器和通信设备有效地最小化由于边缘效应引起的功率损耗，从而具有优异的损耗降低特性。 在电介质基板上形成连续线和多条细长线，每条细长线具有预定长度并从连续线的两侧分支。 利用这种结构，各个细线的边缘基本上不存在，从而可以有效地最小化由于边缘效应引起的损失。

公开(公告)号：US20030133277A1

公开(公告)日：2003-07-17

申请号：US10168403

申请日：2002-11-27

Inventor： Kinji Saijo ,  Kazuo Yoshida ,  Hiroaki Okamoto ,  Shinji Ohsawa

IPC: H01R009/00

CPC classification number: H05K1/0221 ,  H05K3/062 ,  H05K3/4647 ,  H05K2201/0361 ,  H05K2201/09254 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A structure of a multilayer printed wiring board having a wiring lead-out port can be easily formed. A large number of products can be easily manufactured with good size reproducibility. A method of manufacturing the same is also are disclosed. The multilayer printed wiring board is characterized by having a signal circuit conductor perfectly covered by an earth circuit in its inside and a wiring lead-out port. A signal circuit conductor having a branch pattern is preferable. The multilayer printed wiring board is manufactured by selectively etching the copper of a cladding sheet manufactured by bonding a copper foil to a nickel foil with 0.1-3% reduction and forming a signal circuit conductor perfectly covered by an earth circuit and the wiring lead-out port.

Abstract translation: 可以容易地形成具有布线引出口的多层印刷线路板的结构。 可以容易地制造大量的产品，具有良好的尺寸再现性。 还公开了一种制造该方法的方法。 多层印刷电路板的特征在于具有完全被其内部的接地电路覆盖的信号电路导体和布线引出端口。 具有分支图案的信号电路导体是优选的。 多层印刷线路板是通过选择性地蚀刻通过将铜箔结合到镍箔上而制造的包覆片的铜而制造的，所述镍箔具有0.1-3％的还原，并形成完全被接地电路覆盖的信号电路导体和布线引出 港口。

公开(公告)号：US06533587B1

公开(公告)日：2003-03-18

申请号：US09899522

申请日：2001-07-05

Applicant: David Potter ,  Jerry Jarvis ,  Robert Wiley

Inventor： David Potter ,  Jerry Jarvis ,  Robert Wiley

IPC: H01R1200

CPC classification number: G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  G06F1/189 ,  G06F1/20 ,  G11B33/022 ,  G11B33/122 ,  G11B33/142 ,  H01L23/467 ,  H01L2924/0002 ,  H01R12/523 ,  H01R12/7082 ,  H01R12/721 ,  H05K1/0263 ,  H05K1/116 ,  H05K3/325 ,  H05K7/142 ,  H05K7/1444 ,  H05K7/1451 ,  H05K7/1487 ,  H05K2201/09254 ,  H05K2201/10189 ,  H05K2201/10409 ,  H01L2924/00

Abstract: A riser card, such as a peripheral component interconnect (PCI) card, attaches to a circuit board such as a mother board in a transverse orientation and has a first connector and a second connector attached to opposing sides of the card for receiving expansion cards. In one embodiment, the first connector is offset from the second connector with respect to an axis in the plane of the riser card. In another embodiment, the first and second connectors each have a first and last pin, and the first pin of the first card is opposite the first pin of the second connector. The riser card may mount one expansion board right side up, and the second board upside down. The first and second connectors can be female connectors which are each matable with a male connector on the corresponding expansion board, or can be card edge connectors. The expansion boards, when mated with the connectors, are substantially parallel to, but offset from the circuit board. Advantageously, the expansion boards consume less space in the housing by sharing a single riser card, and overall bus length may be substantially reduced between components in addition to providing additional, more open, or better channel space for cooling air flow. A preferred embodiment mounts centrally on a mother board, and provides two side channels for air flow cooling through the chassis of a rack-mounted web server data processor device.

Abstract translation: 诸如外围部件互连（PCI）卡的转接卡卡以横向方式附接到诸如主板的电路板，并且具有附接到卡的相对侧的第一连接器和第二连接器，用于接收扩展卡。 在一个实施例中，第一连接器相对于转接卡的平面中的轴线偏离第二连接器。 在另一个实施例中，第一和第二连接器各自具有第一和最后一个引脚，并且第一卡的第一引脚与第二连接器的第一引脚相对。 转接卡可以将一个扩展板右侧面朝上，第二个板上下颠倒。 第一和第二连接器可以是母连接器，它们均可与相应扩展板上的公连接器配合，或者可以是卡缘连接器。 当与连接器配合时，扩展板基本上平行于电路板，但是偏离电路板。 有利地，扩展板通过共享单个转接卡而消耗在壳体中的较小空间，并且除了为冷却空气流提供附加的，更开放的或更好的通道空间之外，总体总长度可以在部件之间显着减小。 优选实施例集中安装在母板上，并且提供用于通过机架安装的网络服务器数据处理器设备的机箱进行气流冷却的两个侧通道。

公开(公告)号：US20030039105A1

公开(公告)日：2003-02-27

申请号：US10200731

申请日：2002-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myun-Joo Park ,  Byung-Se So ,  Sang-Won Lee ,  Jae-Jun Lee

IPC: H05K001/00 ,  H05K001/18 ,  H05K007/06

CPC classification number: H05K1/0248 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09254

Abstract: A system board includes a control unit; connectors arranged in series in one direction and accepting a connecting means for inputting and outputting data; and signal lines connecting the control unit to the connectors and including at least one branch point, wherein sub signal lines branched off at the same branch point are equal in length and/or loads of path from the branch point to the connecting means.

Abstract translation: 系统板包括控制单元; 连接器在一个方向上串联布置并且接受用于输入和输出数据的连接装置; 以及将控制单元连接到连接器并且包括至少一个分支点的信号线，其中在相同分支点处分支的子信号线在从分支点到连接装置的路径的长度和/或负载相等。

公开(公告)号：US20030016516A1

公开(公告)日：2003-01-23

申请号：US09911754

申请日：2001-07-23

Inventor： James A. McCall ,  Bryce D. Horine ,  Hing Thomas Y. To

IPC: H05K007/06

CPC classification number: H05K1/14 ,  G11C5/04 ,  G11C5/063 ,  H05K1/0246 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022

Abstract: In some embodiments, the invention includes a termination card having a substrate having groups of fingers on a first side of the substrate and groups of fingers on a second side of the substrate and wherein some of the groups of fingers on the first side and some of the groups of fingers on the second side are connected through module connectors, and others of the groups of fingers on the first side are coupled to on module terminations on the first side.

Abstract translation: 在一些实施例中，本发明包括终端卡，其具有在基板的第一侧上具有指状物组的基板和在基板的第二侧上的指状物组，并且其中在第一侧上的一些指状物组 第二侧上的指状物组通过模块连接器连接，并且第一侧上的另一组手指连接到第一侧的模块终端上。

公开(公告)号：US20020176236A1

公开(公告)日：2002-11-28

申请号：US10142203

申请日：2002-05-10

Applicant: FUJI XEROX CO., LTD.

Inventor： Daisuke Iguchi ,  Joji Wakita ,  Kazumi Ikeda ,  Osamu Ueno

IPC: H05K005/00 ,  H05K005/04 ,  H05K005/06

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K9/0039 ,  H05K2201/09245 ,  H05K2201/09254 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/10689

Abstract: A printed wiring board is provided which can be applied even to circuit boards operating at high speed, and which can suppress electromagnetic wave radiation, and which can suppress a deterioration in density of mounting. At the printed wiring board, a first signal wire layer, a first ground layer having a first power source wire, a second ground layer having a second power source wire, and a second signal wire layer, are laminated. The first ground layer and the second ground layer are interlayer-connected by many via holes. Return current, of signal current flowing through a signal wire, flows in the first ground layer, and a path of the return current is cut midway therealong at a position of the first power source wire. However, the return current is detoured by the via hole to the second ground layer, and flows thereat.

Abstract translation: 提供了一种印刷电路板，其可以甚至应用于高速操作的电路板，并且可以抑制电磁波辐射，并且可以抑制安装密度的劣化。 在印刷电路板上层叠有第一信号线层，具有第一电源线的第一接地层，具有第二电源线的第二接地层和第二信号线层。 第一接地层和第二接地层通过许多通孔进行层间连接。 流过信号线的信号电流的返回电流在第一接地层中流动，并且在第一电源线的位置处，中途返回电流的路径被切断。 然而，返回电流被通孔旋转到第二接地层，并在那里流动。

公开(公告)号：US06442057B1

公开(公告)日：2002-08-27

申请号：US09886552

申请日：2001-06-21

Applicant: Won-ki Song ,  Tae-sung Jung

Inventor： Won-ki Song ,  Tae-sung Jung

IPC: G11C506

CPC classification number: H05K1/0248 ,  G06F13/4234 ,  G11C5/063 ,  H05K2201/09254 ,  H05K2201/10159

Abstract: A memory module for preventing skew between bus lines is provided. The memory module includes a printed circuit board, memory chips, module tabs and bus lines. The memory chips are disposed on the printed circuit board, and the module tabs are disposed at one edge of the printed circuit board. The bus lines are connected to the module tabs, respectively, and are connected to the memory chips. Each of the bus lines is formed a closed circuit loop. Each of the bus lines is connected to the memory chips through a circuitous or roundabout path which includes first and second paths of, in general, different lengths. The first and second paths of the roundabout path branch from each other at a position on the closed circuit loop. Since each bus line on the memory module forms a closed loop, skew does not occur between control signals or output data, which are transmitted through the bus line.

公开(公告)号：US06437660B1

公开(公告)日：2002-08-20

申请号：US09698587

申请日：2000-10-27

Applicant: Robert C. Sullivan

Inventor： Robert C. Sullivan

IPC: H01P512

CPC classification number: H05K1/0237 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09254

Abstract: In a backplane interconnect configuration for use in a high-speed data processing system, a plurality of connector slots include an array of connector terminals. First conductive traces electrically couple at least two terminals of adjacent slots, the terminals being coupled by the first conductive traces to form multiple clusters. Each of the plurality of the clusters are in turn electrically coupled by separate conductive traces to at least one common node. This configuration allows for a reduction in the propagation delay of signals propagating between connector slots.

Abstract translation: 在用于高速数据处理系统的背板互连配置中，多个连接器插槽包括连接器端子阵列。 第一导电迹线电耦合相邻槽的至少两个端子，该端子由第一导电迹线耦合以形成多个簇。 多个簇中的每一个依次通过单独的导电迹线电耦合到至少一个公共节点。 该配置允许减少在连接器插槽之间传播的信号的传播延迟。