公开(公告)号：US20140138139A1

公开(公告)日：2014-05-22

申请号：US14079381

申请日：2013-11-13

Applicant: KABUSHIKI KAISHA NIHON MICRONICS

Inventor： Yoshiyuki FUKAMI ,  Toshinori OMORI ,  Katsushi MIKUNI ,  Noriko KON

IPC: H05K3/30 ,  H05K3/46 ,  H05K1/16

CPC classification number: H05K1/167 ,  G01R1/07342 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2891 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K2201/0317 ,  Y10T29/49004 ,  H01L2924/00

Abstract: Provided is a method for manufacturing a multi-layer wiring board and the multi-layer wiring board that are capable of suppressing variation in resistance values. The method according to the present invention is the method for manufacturing a multi-layer wiring board. The method includes forming a resistor thin film, measuring resistance distribution of the resistor thin film, calculating resistor width adjustment rates of the plurality of resistors according to the resistance distribution, forming a pattern of a protective film on the resistor thin film, in which the pattern of the protective pattern has pattern width according to the resistor width adjustment rate, forming a pattern of a plating film on the resistor thin film at a position exposed from the protective film, and etching the resistor thin film at a position exposed from the plating film and the protective film so as to pattern the resistor thin film.

Abstract translation: 提供一种能够抑制电阻值变化的多层布线板和多层布线基板的制造方法。 根据本发明的方法是制造多层布线板的方法。 该方法包括形成电阻薄膜，测量电阻薄膜的电阻分布，根据电阻分布计算多个电阻器的电阻器宽度调节率，在电阻薄膜上形成保护膜的图案，其中 保护图案的图案具有根据电阻器宽度调节率的图案宽度，在从保护膜暴露的位置处在电阻器薄膜上形成电镀膜的图案，并且在暴露于电镀的位置处蚀刻电阻器薄膜 膜和保护膜，以便对电阻薄膜进行图案化。

公开(公告)号：US20140034375A1

公开(公告)日：2014-02-06

申请号：US13566032

申请日：2012-08-03

Applicant: Joseph Kuczynski ,  Melissa K. Miller ,  Heidi D. Williams ,  Jing Zhang

Inventor： Joseph Kuczynski ,  Melissa K. Miller ,  Heidi D. Williams ,  Jing Zhang

IPC: H05K1/11

CPC classification number: H05K3/42 ,  H05K3/421 ,  H05K2201/0317

Abstract: A conductive via and method of forming a conductive via in a multilayer printed circuit board are disclosed. A hole is drilled into a printed circuit board that is reinforced with glass fibers, wherein the hole extends between two conductive elements on different layers of the printed circuit board and cuts through a portion of the glass fibers. A tungsten nitride layer is then deposited on the walls of the hole, wherein the tungsten nitride layer has a thickness between 1.5 nanometers and 20 nanometers. A copper layer is deposited over the tungsten nitride layer, wherein the copper and tungsten nitride form a conductive via that provides an electrically conductive pathway between the two conductive elements, and wherein the tungsten nitride layer isolates the copper layer from the glass fibers.

Abstract translation: 公开了一种在多层印刷电路板中形成导电通孔的导电通孔和方法。 在用玻璃纤维增​​强的印刷电路板上钻出一个孔，其中孔在印刷电路板的不同层上的两个导电元件之间延伸并切割出玻璃纤维的一部分。 然后在孔的壁上沉积氮化钨层，其中氮化钨层具有在1.5纳米和20纳米之间的厚度。 铜层沉积在氮化钨层上，其中铜和氮化钨形成导电通孔，其在两个导电元件之间提供导电通路，并且其中氮化钨层将铜层与玻璃纤维隔离。

公开(公告)号：US20130299216A1

公开(公告)日：2013-11-14

申请号：US13944105

申请日：2013-07-17

Applicant: FUJIFILM Corporation

Inventor： Akira ICHIKI

IPC: H05K1/03

CPC classification number: H05K1/0274 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04112 ,  H05K1/03 ,  H05K3/106 ,  H05K2201/0108 ,  H05K2201/0317 ,  H05K2201/032

Abstract: A transparent electrode sheet includes a transparent support having thereon patterned electrodes, and an absolute value of a difference between a reflection chromaticity of a surface of the electrode of far side from the transparent support and a reflection chromaticity of a surface of the electrode of near side to the transparent support is not more than 2.

Abstract translation: 透明电极片包括其上具有图案化电极的透明支撑体和远侧透明支撑体的电极表面的反射色度与近侧电极表面的反射色度之差的绝对值 对透明支持不超过2。

公开(公告)号：US20130216855A1

公开(公告)日：2013-08-22

申请号：US13823349

申请日：2012-08-30

Applicant: Tomota Nagaura ,  Kazuhiko Sakaguchi

Inventor： Tomota Nagaura ,  Kazuhiko Sakaguchi

IPC: H05K1/09

CPC classification number: H05K1/09 ,  B32B15/01 ,  C23C18/165 ,  C23C18/31 ,  C23C28/023 ,  C25D1/04 ,  C25D3/04 ,  C25D3/12 ,  C25D3/14 ,  C25D3/16 ,  C25D3/38 ,  C25D3/562 ,  C25D3/565 ,  C25D3/58 ,  C25D5/14 ,  C25D7/0614 ,  C25D9/08 ,  C25D11/38 ,  H05K3/025 ,  H05K2201/0317 ,  H05K2201/032 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2203/0307 ,  Y10T428/12438 ,  Y10T428/12493 ,  Y10T428/12514 ,  Y10T428/12611 ,  Y10T428/12667 ,  Y10T428/12861 ,  Y10T428/12882 ,  Y10T428/1291 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/12958 ,  Y10T428/24917

Abstract: The present invention provides a carrier-attached copper foil, wherein an ultrathin copper foil is not peeled from the carrier prior to the lamination to an insulating substrate, but can be peeled from the carrier after the lamination to the insulating substrate. A carrier-attached copper foil comprising a copper foil carrier, an intermediate layer laminated on the copper foil carrier, and an ultrathin copper layer laminated on the intermediate layer, wherein the intermediate foil is configured with a Ni layer in contact with an interface of the copper foil carrier and a Cr layer in contact with an interface of the ultrathin copper layer, said Ni layer containing 1,000-40,000 μg/dm2 of Ni and said Cr layer containing 10-100 μg/dm2 of Cr is provided.

Abstract translation: 本发明提供一种载体附着铜箔，其中在层压到绝缘基板之前，超薄铜箔不从载体剥离，而是可以在与绝缘基板层合之后从载体上剥离。 一种载体附着铜箔，包括铜箔载体，层压在所述铜箔载体上的中间层和层压在所述中间层上的超薄铜层，其中所述中间箔配置有与所述中间层的界面接触的Ni层 铜箔载体和与超薄铜层的界面接触的Cr层，所述Ni层含有1,000-40,000mug / dm 2的Ni，所述Cr层含有10-100mug / dm 2的Cr。

公开(公告)号：US20130114228A1

公开(公告)日：2013-05-09

申请号：US13631156

申请日：2012-09-28

Applicant: Apple Inc.

Inventor： Nicholas G. Merz ,  Hong Wang ,  Michael M. Nikkhoo ,  Dennis R. Pyper ,  Christopher Matthew Werner

IPC: H05K9/00 ,  H05K3/30 ,  H05K7/06

CPC classification number: H05K1/0218 ,  H05K3/284 ,  H05K2201/0317 ,  H05K2201/09618 ,  H05K2201/09872 ,  H05K2201/09909 ,  H05K2201/10371 ,  H05K2201/2018 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: Methods and apparatuses are disclosed for fabricating a printed circuit board (PCB) having electromagnetic interference (EMI) shielding and also having reduced volume over conventional frame-and-shield approaches. Some embodiments include fabricating the PCB by mounting an integrated circuit to the PCB, outlining an area corresponding to the integrated circuit with a number of grounded vias, selectively applying an insulating layer over the PCB such that at least one of the grounded vias are exposed, and selectively applying a conductive layer over the PCB such that the conductive layer covers at least a portion of the integrated circuit and such that the conductive layer is coupled to the at least one of the grounded vias that are exposed.

Abstract translation: 公开了用于制造具有电磁干扰（EMI）屏蔽的印刷电路板（PCB）的方法和装置，并且与传统的框架 - 屏蔽方法相比也具有减小的体积。 一些实施例包括通过将集成电路安装到PCB来制造PCB，通过多个接地通孔来概括对应于集成电路的区域，在PCB上选择性地施加绝缘层，使得接地通孔中的至少一个暴露， 以及选择性地在所述PCB上施加导电层，使得所述导电层覆盖所述集成电路的至少一部分，并且使得所述导电层耦合到暴露的所述接地通孔中的至少一个。

公开(公告)号：US08395091B2

公开(公告)日：2013-03-12

申请号：US12865771

申请日：2009-01-26

Applicant: Philippe Maurin-Perrier ,  Benoit Terme ,  Christophe Heau

Inventor： Philippe Maurin-Perrier ,  Benoit Terme ,  Christophe Heau

IPC: H05B3/00

CPC classification number: H05K1/167 ,  H01C7/006 ,  H01C17/065 ,  H05B3/84 ,  H05B2203/017 ,  H05K1/0212 ,  H05K3/381 ,  H05K2201/0317 ,  H05K2203/025 ,  H05K2203/1115 ,  Y10T29/49083

Abstract: A method for fabricating a heating a element includes modifying the surface state of a substrate in order to obtain at least one smooth area of low roughness and at least one rough area having a higher roughness; applying a highly electrically conductive material to these various areas; and connecting smooth area(s) of the conductive material to an electrical power source.

Abstract translation: 制造加热元件的方法包括改变基底的表面状态以获得至少一个具有较低粗糙度的平滑区域和至少一个具有较高粗糙度的粗糙区域; 将高导电性材料施加到这些不同的区域; 以及将导电材料的平滑区域连接到电源。

公开(公告)号：US08394509B2

公开(公告)日：2013-03-12

申请号：US13002394

申请日：2009-06-26

Applicant: Seiji Nagatani ,  Hiroshi Watanabe ,  Kazufumi Izumida

Inventor： Seiji Nagatani ,  Hiroshi Watanabe ,  Kazufumi Izumida

IPC: B32B15/04

CPC classification number: H05K3/382 ,  B32B15/08 ,  B32B15/20 ,  B32B27/06 ,  B32B2255/06 ,  B32B2255/20 ,  B32B2255/26 ,  B32B2255/28 ,  B32B2307/206 ,  B32B2307/50 ,  B32B2307/538 ,  B32B2307/714 ,  B32B2307/732 ,  B32B2307/75 ,  C23C14/024 ,  C23C14/14 ,  H05K3/388 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0323 ,  Y10T428/12028 ,  Y10T428/12438 ,  Y10T428/12625 ,  Y10T428/12681 ,  Y10T428/12806 ,  Y10T428/12903 ,  Y10T428/24975 ,  Y10T428/265

Abstract: Object is to provide a surface-treated copper foil free from chromium in the surface-treatment layer and excellent in peel strength of a circuit and chemical resistance against to degradation of the peel strength after processing into a printed wiring board. To achieve the object, the surface-treated copper foil having a surface-treatment layer on a bonding surface of a copper foil for manufacturing a copper-clad laminate by laminating it to an insulating resin substrate has the surface-treatment layer formed by depositing a metal component having high melting point not lower than 1400° C. by dry process film formation method to the bonding surface of the copper foil after the cleaning treatment and further depositing a carbon component to the surface.

Abstract translation: 本发明提供一种在表面处理层中不含铬的表面处理铜箔，并且电路的剥离强度优异，并且在加工成印刷线路板之后，耐化学性能降低剥离强度。 为了实现该目的，在覆铜层压板的制造用铜箔的接合面上具有表面处理层的表面处理铜箔通过层叠在绝缘性树脂基板上而形成有表面处理层， 通过干法成膜法将熔点不低于1400℃的高熔点金属成分施加到清洁处理后的铜箔的接合面上，并进一步在表面上沉积碳成分。

公开(公告)号：US20130032383A1

公开(公告)日：2013-02-07

申请号：US13548575

申请日：2012-07-13

Applicant: Won Hee Yoo ,  Byeung Gyu Chang ,  Taek Jung Lee ,  Yun Hwi Park

Inventor： Won Hee Yoo ,  Byeung Gyu Chang ,  Taek Jung Lee ,  Yun Hwi Park

IPC: H05K1/03 ,  B05D3/10

CPC classification number: H05K3/06 ,  H05K1/03 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/02 ,  H05K3/107 ,  H05K2201/0317 ,  H05K2203/025

Abstract: Disclosed herein are a thin film electrode ceramic substrate and a method for manufacturing the same. The thin film electrode ceramic substrate includes: a ceramic substrate; one or more anti-etching metal layers formed in a surface of the ceramic substrate; thin film electrode pattern formed on the anti-etching metal layers; and a plating layer formed on the thin film electrode pattern, wherein respective edge portions of the thin film electrode pattern are contacted with the anti-etching metal layer, and thus, an undercut defect occurring between the surface of the ceramic substrate and the thin film electrode pattern and between the thin film electrode patterns due to an etchant can be prevented and the binding strength of the entire thin film electrode pattern can be enhanced, resulting in securing durability and reliability of the thin film electrode patterns.

Abstract translation: 本文公开了一种薄膜电极陶瓷基板及其制造方法。 薄膜电极陶瓷基板包括：陶瓷基板; 形成在陶瓷基板的表面上的一个或多个抗蚀刻金属层; 在抗蚀刻金属层上形成的薄膜电极图案; 以及形成在薄膜电极图案上的镀层，其中薄膜电极图案的各个边缘部分与抗蚀刻金属层接触，因此在陶瓷基板的表面和薄膜之间发生切削缺陷 可以防止由于蚀刻剂引起的薄膜电极图案之间的电极图案和薄膜电极图案之间的粘合强度，从而确保薄膜电极图案的耐久性和可靠性。

公开(公告)号：US08354009B2

公开(公告)日：2013-01-15

申请号：US12034707

申请日：2008-02-21

Applicant: Jeon Geon Han ,  Kab Seog Kim ,  Yong Mo Kim

Inventor： Jeon Geon Han ,  Kab Seog Kim ,  Yong Mo Kim

IPC: C23C14/00

CPC classification number: C23C14/352 ,  C23C14/20 ,  C23C14/562 ,  H01J37/3277 ,  H01J37/3405 ,  H05K1/028 ,  H05K1/09 ,  H05K3/16 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2203/1476 ,  H05K2203/1545

Abstract: An apparatus and method for manufacturing a highly efficient flexible thin metal film-laminated strip by improves adhesiveness between a polyimide strip and a thin metal film, and removes stress from thin films laminated through magnetron sputtering, which is a dry deposition process. The stress-free flexible circuit board manufacturing method includes the steps of: a) depositing a seed layer on the substrate using the magnetron deposition source; b) depositing a compressive thin film using the single magnetron deposition source arranged next to the magnetron deposition source; c) depositing tensile thin film using the dual magnetron deposition source arranged next to the single magnetron deposition source; and d) repeating the steps b) and c) so as to sequentially and alternately deposit compressive thin films and tensile thin films thereby obtaining a thick film with a desired thickness.

Abstract translation: 通过改善聚酰亚胺条和薄金属膜之间的粘合性，并且通过作为干沉积工艺的磁控溅射层叠的薄膜来消除应力，从而制造高效率的柔性薄金属膜层叠带的装置和方法。 无应力柔性电路板的制造方法包括以下步骤：a）使用磁控管沉积源将种子层沉积在基板上; b）使用布置在磁控管沉积源旁边的单个磁控管沉积源沉积压缩薄膜; c）使用布置在单个磁控管沉积源旁边的双重磁控管沉积源沉积拉伸薄膜; 以及d）重复步骤b）和c），以顺序和交替地沉积压缩薄膜和拉伸薄膜，从而获得具有所需厚度的厚膜。

公开(公告)号：US08318032B2

公开(公告)日：2012-11-27

申请号：US11962164

申请日：2007-12-21

Applicant: John B. Szczech ,  Daniel R. Gamota ,  Tomasz L. Klosowiak ,  Jerzy Wielgus

Inventor： John B. Szczech ,  Daniel R. Gamota ,  Tomasz L. Klosowiak ,  Jerzy Wielgus

IPC: B44C1/22

CPC classification number: H05K3/027 ,  H05K1/0393 ,  H05K3/16 ,  H05K2201/0116 ,  H05K2201/0317 ,  H05K2201/10113 ,  H05K2203/0557 ,  H05K2203/056

Abstract: A method for delineating a metallization pattern in a layer of sputtered aluminum or sputtered copper using a broad spectrum high intensity light source. The metal is deposited on a polymeric substrate by sputtering, so that it has a porous nanostructure. An opaque mask that is a positive representation of the desired metallization pattern is then situated over the metallization layer, exposing those portions of the metallization layer intended to be removed. The masked metallization layer is then exposed to a rapid burst of high intensity visible light from an arc source sufficient to cause complete removal of the exposed portions of the metallization layer, exposing the underlying substrate and creating the delineated pattern.

Abstract translation: 使用广谱高强度光源描绘溅射铝或溅射铜层中的金属化图案的方法。 通过溅射将金属沉积在聚合物基底上，使其具有多孔纳米结构。 然后将作为所需金属化图案的正表示的不透明掩模放置在金属化层上方，暴露预期要去除的金属化层的那些部分。 掩蔽的金属化层然后暴露于来自电弧源的高强度可见光的快速爆发，足以引起金属化层的暴露部分的完全去除，暴露下面的衬底并产生描绘图案。